Routing Reference¶

`AddrRange` ¶

Bases: BaseModel

Address range class.

`set_arr(arr_idx, arr_dim)` ¶

Update the address range with the given index.

`validate_input()` ¶

Validate the address range.

`validate_output()` ¶

Validate the address range.

`CollectiveCfg` ¶

Bases: BaseModel

User-facing collective operation configuration.

The five high-level knobs map to collective_cfg_t in floo_pkg:

+-----------------------+--------------------------------------------+ | YAML field | floo_pkg bits set | +=======================+============================================+ | en_narrow_multicast | OpCfg.EnNarrowMulticast | | en_wide_multicast | OpCfg.EnWideMulticast | | en_barrier | OpCfg.EnLsbAnd | | en_narrow_reduction | OpCfg.EnA_{Add,Mul,MinS,MinU,MaxS,MaxU} | | en_wide_reduction | OpCfg.EnF_{Add,Mul,Min,Max} | +-----------------------+--------------------------------------------+

For en_narrow_reduction / en_wide_reduction: - false / omitted → disabled (default) - true → all ops enabled, default hw config - [Add, Mul, ...] → only the listed ops, default hw config - {ops: [...], rd_pipeline_depth: N, cut_offload_intf: true} → full per-channel control

`en_collective` `property` ¶

True when any collective feature is enabled (multicast, barrier, or reduction).

`get_collective_cfg` `property` ¶

Return a dict representing collective_cfg_t for sv_struct_render.

`render_reduction_typedefs(cfg_n, cfg_w)` ¶

Render offload reduction channel/link typedefs for enabled channels.

`Coord` ¶

Bases: BaseModel

2D coordinate class.

`from_dict(coord_dict)` `staticmethod` ¶

Create a Coord object from a dictionary.

`get_dir(node, neighbor)` `staticmethod` ¶

Get the direction from node to neighbor.

`render(as_index=False)` ¶

Render the SystemVerilog coordinate.

`NarrowReductionCfg` ¶

Bases: ReductionCfg

Reduction configuration for the narrow link.

`get_reduction_cfg()` ¶

Return a dict representing reduction_cfg_t for sv_struct_render.

`NarrowReductionOp` ¶

Bases: Enum

Integer ALU reduction operations available on the narrow router.

`ReductionCfg` ¶

Bases: BaseModel

Base reduction hardware configuration shared by narrow and wide channels.

`get_reduction_cfg()` ¶

Return a dict representing reduction_cfg_t for sv_struct_render.

`RouteAlgo` ¶

Bases: Enum

Routing algorithm enum.

`RouteMap` ¶

Bases: BaseModel

Route Map class, which can represent the system address map (SAM), or a routing table of a router.

`check_no_overlapping_ranges()` ¶

Check if there are no overlapping ranges.

`pprint()` ¶

Pretty print the routing table.

`render(aw=None)` ¶

Render the SystemVerilog routing table.

`render_rdl(rdl_as_mem=False, rdl_memwidth=8)` ¶

Render the SystemRDL addrmap internals.

`render_rdl_inc()` ¶

Render the SystemRDL include header.

`rule_type()` ¶

Return the type of the rules.

`trim()` ¶

Optimize the routing table.

`RouteMapRule` ¶

Bases: BaseModel

Routing rule class.

`get_rdl(instance_name, rdl_as_mem=False, rdl_memwidth=8)` ¶

Render the SystemRDL routing rule.

`render(aw=None)` ¶

Render the SystemVerilog routing rule.

`render_desc()` ¶

Render the description of the routing rule.

`RouteMapRuleCollective` ¶

Bases: RouteMapRule

Routing rule class for collective operations (multicast, reduction, barrier).

`get_rdl(instance_name, rdl_as_mem=False, rdl_memwidth=8)` ¶

Render the SystemRDL routing rule.

`render(aw=None)` ¶

Render the SystemVerilog routing rule.

`render_desc()` ¶

Render the description of the routing rule.

`RouteRule` ¶

Bases: BaseModel

Routing rule class.

`render(num_route_bits)` ¶

Render the SystemVerilog route.

`RouteTable` ¶

Bases: BaseModel

Route Table class, which can hold the route entries to each destination

`render(num_route_bits, no_decl=False)` ¶

Render the SystemVerilog route table.

`sort_and_pad()` ¶

Sort by destination and fill in missing entries.

`Routing` ¶

Bases: BaseModel

The class that holds essentially all the routing information needed.

Attributes:

Name	Type	Description
`route_algo`	`RouteAlgo`	The routing algorithm to use. See RouteAlgo enum for the options.
`use_id_table`	`bool`	Whether to use a table to decode the destination ID.
`sam`	`RouteMap`	The system address map.
`table`	`RouteMap`	The routing table of the router.
`addr_offset_bits`	`int`	The number of bits to decode the X and Y coordinates from the address. Only used if `use_id_table` is False and `route_algo` is XY.
`xy_id_offset`	`Union[SimpleId, Coord]`	A constant offset to add to the X and Y coordinates. Only used if `route_algo` is XY.
`num_endpoints`	`int`	The number of endpoints in the network.
`num_id_bits`	`int`	The number of bits to represent the ID. Only used if `route_algo` is ID or SRC.
`num_x_bits`	`int`	The number of bits to represent the X coordinate. Only used if `route_algo` is XY.
`num_y_bits`	`int`	The number of bits to represent the Y coordinate. Only used if `route_algo` is XY.
`num_route_bits`	`int`	The number of bits to represent the route. Only used if `route_algo` is SRC.
`addr_width`	`int`	The width of the address bus.
`rob_idx_bits`	`int`	The number of bits to represent the reorder buffer index.
`port_id_bits`	`int`	The number of bits to represent the local port ID.
`collective`	`CollectiveCfg`	Collective operation configuration (multicast, barrier, reduction).
`collective_sam`	`RouteMap`	The collective system address map. Only used if collective is enabled.

`en_collective` `property` ¶

True when any collective feature is enabled (multicast, barrier, or reduction).

`render_hdr_typedef(network_type)` ¶

Render the SystemVerilog flit header.

`render_param_decl()` ¶

Render the SystemVerilog parameter declaration.

`render_route_cfg(name)` ¶

Render the SystemVerilog routing configuration.

`render_typedefs()` ¶

Render the SystemVerilog typedefs.

`render_vc_impl()` ¶

Render WideRwDecouple and VcImpl localparam declarations.

`validate_collective_route_algo()` ¶

Collective operations are supported with XY routing only.

`validate_decouple_rw(v)` `classmethod` ¶

Accept bool (False→NONE) or string/enum name.

`validate_route_algo(v)` `classmethod` ¶

Validate the routing algorithm.

`validate_vc_impl(v)` `classmethod` ¶

Accept both enum members and string names.

`SimpleId` ¶

Bases: BaseModel

ID class.

`add(other)` ¶

Add the ID.

`lt(other)` ¶

Less than comparison.

`sub(other)` ¶

Subtract the ID.

`render(as_index=False)` ¶

Render the SystemVerilog ID.

`validate_id(v)` `classmethod` ¶

Validate the ID.

`VcImpl` ¶

Bases: Enum

Virtual channel implementation enum (mirrors vc_impl_e in floo_pkg).

Only relevant when decouple_rw == WideRwDecouple.VC.

`WideReductionCfg` ¶

Bases: ReductionCfg

Reduction configuration for the wide link.

`get_reduction_cfg()` ¶

Return a dict representing reduction_cfg_t for sv_struct_render.

`WideReductionOp` ¶

Bases: Enum

Floating-point reduction operations available on the wide router.

`WideRwDecouple` ¶

Bases: Enum

Read/write decoupling mode for the wide link (mirrors wide_rw_decouple_e in floo_pkg).

NONE — shared wide link, no decoupling (default) VC — decouple using virtual channels (requires vc_impl) PHYS — decouple using separate physical wide links

`XYDirections` ¶

Bases: Enum

XY directions enum.

`reverse(direction)` `classmethod` ¶

Reverse the direction.

`to_coords(direction)` `classmethod` ¶

Convert the direction to coordinates.

Routing Reference¶

AddrRange ¶

set_arr(arr_idx, arr_dim) ¶

validate_input() ¶

validate_output() ¶

CollectiveCfg ¶

en_collective property ¶

get_collective_cfg property ¶

render_reduction_typedefs(cfg_n, cfg_w) ¶

Coord ¶

from_dict(coord_dict) staticmethod ¶

get_dir(node, neighbor) staticmethod ¶

render(as_index=False) ¶

NarrowReductionCfg ¶

get_reduction_cfg() ¶

NarrowReductionOp ¶

ReductionCfg ¶

get_reduction_cfg() ¶

RouteAlgo ¶

RouteMap ¶

check_no_overlapping_ranges() ¶

pprint() ¶

render(aw=None) ¶

render_rdl(rdl_as_mem=False, rdl_memwidth=8) ¶

render_rdl_inc() ¶

rule_type() ¶

trim() ¶

RouteMapRule ¶

get_rdl(instance_name, rdl_as_mem=False, rdl_memwidth=8) ¶

render(aw=None) ¶

render_desc() ¶

RouteMapRuleCollective ¶

get_rdl(instance_name, rdl_as_mem=False, rdl_memwidth=8) ¶

render(aw=None) ¶

render_desc() ¶

RouteRule ¶

render(num_route_bits) ¶

RouteTable ¶

render(num_route_bits, no_decl=False) ¶

sort_and_pad() ¶

Routing ¶

en_collective property ¶

render_hdr_typedef(network_type) ¶

render_param_decl() ¶

render_route_cfg(name) ¶

render_typedefs() ¶

render_vc_impl() ¶

validate_collective_route_algo() ¶

validate_decouple_rw(v) classmethod ¶

validate_route_algo(v) classmethod ¶

validate_vc_impl(v) classmethod ¶

SimpleId ¶

__add__(other) ¶

__lt__(other) ¶

__sub__(other) ¶

render(as_index=False) ¶

validate_id(v) classmethod ¶

VcImpl ¶

WideReductionCfg ¶

get_reduction_cfg() ¶

WideReductionOp ¶

WideRwDecouple ¶

XYDirections ¶

reverse(direction) classmethod ¶

to_coords(direction) classmethod ¶

`AddrRange` ¶

`set_arr(arr_idx, arr_dim)` ¶

`validate_input()` ¶

`validate_output()` ¶

`CollectiveCfg` ¶

`en_collective` `property` ¶

`get_collective_cfg` `property` ¶

`render_reduction_typedefs(cfg_n, cfg_w)` ¶

`Coord` ¶

`from_dict(coord_dict)` `staticmethod` ¶

`get_dir(node, neighbor)` `staticmethod` ¶

`render(as_index=False)` ¶

`NarrowReductionCfg` ¶

`get_reduction_cfg()` ¶

`NarrowReductionOp` ¶

`ReductionCfg` ¶

`get_reduction_cfg()` ¶

`RouteAlgo` ¶

`RouteMap` ¶

`check_no_overlapping_ranges()` ¶

`pprint()` ¶

`render(aw=None)` ¶

`render_rdl(rdl_as_mem=False, rdl_memwidth=8)` ¶

`render_rdl_inc()` ¶

`rule_type()` ¶

`trim()` ¶

`RouteMapRule` ¶

`get_rdl(instance_name, rdl_as_mem=False, rdl_memwidth=8)` ¶

`render(aw=None)` ¶

`render_desc()` ¶

`RouteMapRuleCollective` ¶

`get_rdl(instance_name, rdl_as_mem=False, rdl_memwidth=8)` ¶

`render(aw=None)` ¶

`render_desc()` ¶

`RouteRule` ¶

`render(num_route_bits)` ¶

`RouteTable` ¶

`render(num_route_bits, no_decl=False)` ¶

`sort_and_pad()` ¶

`Routing` ¶

`en_collective` `property` ¶

`render_hdr_typedef(network_type)` ¶

`render_param_decl()` ¶

`render_route_cfg(name)` ¶

`render_typedefs()` ¶

`render_vc_impl()` ¶

`validate_collective_route_algo()` ¶

`validate_decouple_rw(v)` `classmethod` ¶

`validate_route_algo(v)` `classmethod` ¶

`validate_vc_impl(v)` `classmethod` ¶

`SimpleId` ¶

`add(other)` ¶

`lt(other)` ¶

`sub(other)` ¶

`render(as_index=False)` ¶

`validate_id(v)` `classmethod` ¶

`VcImpl` ¶

`WideReductionCfg` ¶

`get_reduction_cfg()` ¶

`WideReductionOp` ¶

`WideRwDecouple` ¶

`XYDirections` ¶

`reverse(direction)` `classmethod` ¶

`to_coords(direction)` `classmethod` ¶