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Utility Functions Reference

A collection of utility functions. Most of them are used internally by FlooGen to render SystemVerilog templates.

bool_to_sv(value)

Converts a boolean to a SystemVerilog string.

Examples:

>>> bool_to_sv(True)
"1'b1"

Parameters:

Name Type Description Default
value bool

Input boolean value.

 required

Returns:

Name Type Description
str str

"1'b1" if True, "1'b0" if False.

camel_to_snake(name)

Converts a camel case string to snake case.

Examples:

>>> camel_to_snake("CamelCase")
'camel_case'

Parameters:

Name Type Description Default
name str

Input camel case string.

 required

Returns:

Name Type Description
str str

Converted snake case string.

cdiv(x, y)

Compute the ceiling of x / y.

Examples:

>>> cdiv(7, 2)
4

Parameters:

Name Type Description Default
x (int, float)

Numerator.

 required
y (int, float)

Denominator.

 required

Returns:

Name Type Description
int int

Ceiling of x / y.

clog2(x)

Returns the ceiling of log2(x).

Examples:

>>> clog2(7)
3

Parameters:

Name Type Description Default
x int

Input value.

 required

Returns:

Name Type Description
int int

Ceiling of log2(x).

int_to_hex(value, width)

Converts an integer to a hex string.

Examples:

>>> int_to_hex(255, 8)
"8'hff"

Parameters:

Name Type Description Default
value int

Input integer value.

 required
width int

Bit width of the value.

 required

Returns:

Name Type Description
str str

Hex string representation of the integer.

short_dir(direction)

Returns the short direction string.

Parameters:

Name Type Description Default
direction str

"input" or "output".

 required

Returns:

Name Type Description
str str

"in" or "out".

snake_to_camel(name)

Converts a snake case string to camel case.

Examples:

>>> snake_to_camel("snake_case")
'SnakeCase'

Parameters:

Name Type Description Default
name str

Input snake case string.

 required

Returns:

Name Type Description
str str

Converted camel case string.

sv_enum_typedef(name, fields_dict=None, fields_list=None)

Declare a SystemVerilog enum typedef.

Examples:

>>> sv_enum_typedef("my_enum_e", fields_list=["field_one", "field_two"])
"typedef enum logic[0:0] {
    FieldOne = 0,
    FieldTwo = 1
} my_enum_e;"
>>> sv_enum_typedef("my_enum_e", fields_dict={"field_one": 4, "field_two": 6})
"typedef enum logic[2:0] {
    FieldOne = 4,
    FieldTwo = 6
} my_enum_e;"

Parameters:

Name Type Description Default
name str

Name of the enum typedef.

 required
fields_dict dict

Dictionary of field names and their corresponding values. Defaults to None.

 None
fields_list list

List of field names. Values will be assigned automatically starting from 0. Defaults to None.

 None

Returns:

Name Type Description
str str

SystemVerilog enum typedef declaration.

sv_param_decl(name, value, ptype='localparam', dtype='int unsigned', array_size=None)

Declare a SystemVerilog parameter.

Examples:

>>> sv_param_decl("Width", 8)
"localparam int unsigned Width = 8;"
>>> sv_param_decl("Depth", 16, ptype="parameter", dtype="my_type_t", array_size=4)
"parameter my_type_t [3:0] Depth = 16;"

Parameters:

Name Type Description Default
name str

Name of the parameter.

 required
value (int, str)

Value of the parameter.

 required
ptype str

Type of the parameter, either "localparam" or "parameter". Defaults to "localparam".

 'localparam'
dtype str

Data type of the parameter. Defaults to "int unsigned".

 'int unsigned'
array_size (int, str, list)

Size of the array. Can be an integer, a string (for expressions), or a list of integers/strings for multi-dimensional arrays. Defaults to None.

 None

Returns:

Name Type Description
str str

SystemVerilog parameter declaration.

sv_struct_render(fields)

Declare a SystemVerilog struct based on a (nested) dictionary, where they keys of the dictionary are the field names, and the values are the actual values to assign.

Example

fields = {'field1': '3'd0', 'field2': {'subfield1': 'some_signal', 'subfield2': 'SomeParam'}} sv_struct_render(fields) -> '{ field1: 3'd0, field2: '{ subfield1: some_signal, subfield2: SomeParam }, }'

sv_struct_typedef(name, fields, union=False)

Declare a SystemVerilog struct typedef.

sv_typedef(name, dtype='logic', array_size=None)

Declare a SystemVerilog typedef.

Examples:

>>> sv_typedef("my_type_t", "logic", 8)
"typedef logic[7:0] my_type_t;"

Parameters:

Name Type Description Default
name str

Name of the typedef.

 required
dtype str

Data type of the typedef. Defaults to "logic".

 'logic'
array_size int

Size of the array. If None, a scalar type is declared. Defaults to None.

 None

Returns:

Name Type Description
str str

SystemVerilog typedef declaration.

verible_format(string, verible_fmt_bin=None, verible_fmt_args=None)

Format the string using verible-verilog-format.

Parameters:

Name Type Description Default
string str

Input string to format.

 required
verible_fmt_bin str

Path to the verible-verilog-format binary. If None, it will try to find it in the PATH. Defaults to None.

 None
verible_fmt_args str

Additional arguments to pass to verible-verilog-format. If None, no additional arguments are passed. Defaults to None.

 None

Returns:

Name Type Description
str str

Formatted string, or the original string if verible-verilog-format is not found.