# `segment_sequencer` - Split segment memory operations into multiple micro-ops

This module breaks down segment memory operations into a sequence of scalar memory operations. While this results in poor instruction-per-cycle (IPC) performance, it simplifies hardware implementation and avoids the need for tightly coupled multi-element memory accesses.

## Key Parameters

- `SegSupport`: Enables or disables segment memory support (`1'b1` enables it).
- `ara_req_t`, `ara_resp_t`: Types representing Ara's request and response protocols.

## Interface Signals

### Clock & Reset
- `clk_i`: Clock signal.
- `rst_ni`: Active-low reset.

### Control Inputs
- `ara_idle_i`: Indicates Ara is idle.
- `is_segment_mem_op_i`: Indicates the instruction is a segment memory op.
- `illegal_insn_i`: Signals if the instruction is illegal.
- `is_vload_i`: Identifies if the operation is a vector load.

### Operation Tracking
- `seg_mem_op_end_o`: Signals the end of a segment memory op.
- `load_complete_i/o`, `store_complete_i/o`: Track completion of memory operations.

### Ara Frontend-Backend Interface
- `ara_req_i/o`, `ara_req_valid_i/o`, `ara_req_ready_i`
- `ara_resp_i/o`, `ara_resp_valid_i/o`

## Functionality

When `SegSupport` is enabled, this module implements a small FSM to micro-sequence a segment operation into a series of scalar instructions. These instructions are prepared by adjusting `vs1`, `vd`, and `scalar_op` fields, and issuing one sub-operation at a time.

### FSM States

- `IDLE`: Wait for segment memory op. Sample `nf` and `is_vload_i`.
- `SEGMENT_MICRO_OPS`: Sequentially issue micro-operations for each field of the segment.
- `SEGMENT_MICRO_OPS_WAIT_END`: Wait for Ara backend to become idle.
- `SEGMENT_MICRO_OPS_END`: Forward the final response and signal completion.

### Micro-operation Construction

- For each segment element:
  - `vl` is set to 1
  - `vstart` tracks the segment index
  - `vs1`, `vd`, and `scalar_op` are offset by the segment field index (`segment_cnt_q`)
- For unit-stride segments (`VLE`, `VSE`): `op` is changed to `VLSE`, `VSSE` and a `stride` is computed.

### Control Logic

- Two counters are used:
  - `segment_cnt_q` tracks the number of fields processed
  - `vstart_cnt_q` increments for each segment
- Response (`ara_resp_q`) is delayed until the full operation finishes and Ara is idle.

## Disabled Mode (SegSupport == 0)

In this case, the module becomes a passthrough between Ara's frontend and backend, with no internal FSM or micro-operation handling.