Documentation

Contains all necessary type definitions, constants, and generally useful functions.

A set of testbench utilities for AXI interfaces.

Filter atomic operations (ATOPs) in a protocol-compliant manner.

Interface variant of axi_atop_filter.

Split AXI4 bursts into single-beat transactions.

Internal module of axi_burst_splitter to control Ax channels.

Internal module of axi_burst_splitter to order transactions.

Synthesizable test module comparing two AXI channels of the same type

A clock domain crossing on an AXI interface.

Destination-clock-domain half of the AXI CDC crossing.

Source-clock-domain half of the AXI CDC crossing.

Non-synthesizable module comparing two AXI channels of the same type

An AXI4 cut.

Synthesizable module that (randomly) delays AXI channels.

Demultiplex one AXI4+ATOP slave port to multiple AXI4+ATOP master ports.

Demultiplex one AXI4+ATOP slave port to multiple AXI4+ATOP master ports.

Simulation-Only dumper for AXI transactions

Protocol adapter which translates memory requests to the AXI4 protocol.

Remap AXI IDs from wide IDs at the slave port to narrower IDs at the master port.

Internal module of axi_id_remap: Table to remap input to output IDs.

Interface variant of axi_id_remap.

Reduce AXI IDs by serializing transactions when necessary.

Interface variant of axi_id_serialize.

Interleaved version of the crossbar. This module is experimental; use at your own risk.

This module can isolate the AXI4+ATOPs bus on the master port from the slave port. When the

Interface variant of axi_isolate.

Convert between any two AXI ID widths.

Interface variant of axi_iw_converter.

A connector that joins two AXI interfaces.

AXI4 LFSR Subordinate device. Responds with a pseudo random answer. Serial interface to

Protocol adapter which translates memory requests to the AXI4-Lite protocol.

A connector that joins two AXI-Lite interfaces.

AXI4 Lite LFSR Subordinate device. Responds with a pseudo random answer. Serial interface to

XOR LFSR with tabs based on the lfsr_table. LFSR has

AXI4-Lite registers with optional read-only and protection features.

Interface variant of axi_lite_regs.

An AXI4-Lite to AXI4 adapter.

Modify addresses on an AXI4 bus

Interface variant of axi_modify_address

Joins a read and a write slave into one single read / write master

Splits a single read / write slave into one read and one write master

Serialize all AXI transactions to a single ID (zero).

Serialize all AXI transactions to a single ID (zero), interface version.

Infinite (Simulation-Only) Memory with AXI Slave Port

Interface variant of axi_sim_mem.

Mutliport interface variant of axi_sim_mem.

Synthesizable test module comparing two AXI slaves of the same type.

Throttles an AXI4+ATOP bus. The maximum number of outstanding transfers have to

An AXI4+ATOP to AXI4-Lite converter with atomic transaction and burst support.

AXI4+ATOP slave module which translates AXI bursts into a memory stream.

Interface wrapper for module axi_to_mem.

AXI4+ATOP slave module which translates AXI bursts into a memory stream.

Interface wrapper for module axi_to_mem.

AXI4+ATOP to banked SRAM memory slave. Allows for parallel read and write transactions.

AXI4+ATOP interface wrapper for axi_to_mem

AXI4+ATOP to SRAM memory slave. Allows for parallel read and write transactions.

AXI4+ATOP interface wrapper for axi_to_mem_interleaved

AXI4+ATOP to memory-protocol interconnect. Completely separates the read and write channel to

AXI4+ATOP interface wrapper for axi_to_mem_split

axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports.

axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports.

AXI Crosspoint (XP) with homomorphous slave and master ports.

AXI4+ATOP slave module which translates AXI bursts into a memory stream