Documentation

Packages

axi_pkg

Contains all necessary type definitions, constants, and generally useful functions.

axi_test

A set of testbench utilities for AXI interfaces.

Modules

axi_atop_filter

Filter atomic operations (ATOPs) in a protocol-compliant manner.

axi_atop_filter_intf

Interface variant of axi_atop_filter.

axi_burst_splitter

Split AXI4 bursts into single-beat transactions.

axi_burst_splitter_ax_chan

Internal module of axi_burst_splitter to control Ax channels.

axi_burst_splitter_counters

Internal module of axi_burst_splitter to order transactions.

axi_bus_compare

Synthesizable test module comparing two AXI channels of the same type

axi_cdc

A clock domain crossing on an AXI interface.

axi_cdc_intf
axi_lite_cdc_intf
axi_cdc_dst

Destination-clock-domain half of the AXI CDC crossing.

axi_cdc_dst_intf
axi_lite_cdc_dst_intf
axi_cdc_src

Source-clock-domain half of the AXI CDC crossing.

axi_cdc_src_intf
axi_lite_cdc_src_intf
axi_chan_compare

Non-synthesizable module comparing two AXI channels of the same type

axi_cut

An AXI4 cut.

axi_cut_intf
axi_lite_cut_intf
axi_delayer

Synthesizable module that (randomly) delays AXI channels.

axi_delayer_intf
axi_demux

Demultiplex one AXI4+ATOP slave port to multiple AXI4+ATOP master ports.

axi_demux_intf
axi_demux_simple

Demultiplex one AXI4+ATOP slave port to multiple AXI4+ATOP master ports.

axi_demux_id_counters
axi_dumper

Simulation-Only dumper for AXI transactions

axi_dumper_intf
axi_dw_converter
axi_dw_converter_intf
axi_dw_downsizer
axi_dw_upsizer
axi_err_slv
axi_fifo
axi_fifo_intf
axi_from_mem

Protocol adapter which translates memory requests to the AXI4 protocol.

axi_id_prepend
axi_id_remap

Remap AXI IDs from wide IDs at the slave port to narrower IDs at the master port.

axi_id_remap_table

Internal module of axi_id_remap: Table to remap input to output IDs.

axi_id_remap_intf

Interface variant of axi_id_remap.

axi_id_serialize

Reduce AXI IDs by serializing transactions when necessary.

axi_id_serialize_intf

Interface variant of axi_id_serialize.

axi_interleaved_xbar

Interleaved version of the crossbar. This module is experimental; use at your own risk.

axi_interleaved_xbar_intf
axi_isolate

This module can isolate the AXI4+ATOPs bus on the master port from the slave port. When the

axi_isolate_inner
axi_isolate_intf

Interface variant of axi_isolate.

axi_iw_converter

Convert between any two AXI ID widths.

axi_iw_converter_intf

Interface variant of axi_iw_converter.

axi_join_intf

A connector that joins two AXI interfaces.

axi_lfsr

AXI4 LFSR Subordinate device. Responds with a pseudo random answer. Serial interface to

axi_lite_demux
axi_lite_demux_intf
axi_lite_dw_converter
axi_lite_dw_converter_intf
axi_lite_from_mem

Protocol adapter which translates memory requests to the AXI4-Lite protocol.

axi_lite_join_intf

A connector that joins two AXI-Lite interfaces.

axi_lite_lfsr

AXI4 Lite LFSR Subordinate device. Responds with a pseudo random answer. Serial interface to

axi_opt_lfsr

XOR LFSR with tabs based on the lfsr_table. LFSR has

axi_lite_mailbox
axi_lite_mailbox_slave
axi_lite_mailbox_intf
axi_lite_mux
axi_lite_mux_intf
axi_lite_regs

AXI4-Lite registers with optional read-only and protection features.

axi_lite_regs_intf

Interface variant of axi_lite_regs.

axi_lite_to_apb
axi_lite_to_apb_intf
axi_lite_to_axi

An AXI4-Lite to AXI4 adapter.

axi_lite_to_axi_intf
axi_lite_xbar
axi_lite_xbar_intf
axi_modify_address

Modify addresses on an AXI4 bus

axi_modify_address_intf

Interface variant of axi_modify_address

axi_multicut
axi_multicut_intf
axi_lite_multicut_intf
axi_mux
axi_mux_intf
axi_rw_join

Joins a read and a write slave into one single read / write master

axi_rw_split

Splits a single read / write slave into one read and one write master

axi_serializer

Serialize all AXI transactions to a single ID (zero).

axi_serializer_intf

Serialize all AXI transactions to a single ID (zero), interface version.

axi_sim_mem

Infinite (Simulation-Only) Memory with AXI Slave Port

axi_sim_mem_intf

Interface variant of axi_sim_mem.

axi_slave_compare

Synthesizable test module comparing two AXI slaves of the same type.

axi_chan_logger
axi_throttle

Throttles an AXI4+ATOP bus. The maximum number of outstanding transfers have to

axi_to_axi_lite

An AXI4+ATOP to AXI4-Lite converter with atomic transaction and burst support.

axi_to_axi_lite_id_reflect
axi_to_axi_lite_intf
axi_to_detailed_mem

AXI4+ATOP slave module which translates AXI bursts into a memory stream.

axi_to_detailed_mem_intf

Interface wrapper for module axi_to_mem.

axi_to_mem

AXI4+ATOP slave module which translates AXI bursts into a memory stream.

axi_to_mem_intf

Interface wrapper for module axi_to_mem.

axi_to_mem_banked

AXI4+ATOP to banked SRAM memory slave. Allows for parallel read and write transactions.

axi_to_mem_banked_intf

AXI4+ATOP interface wrapper for axi_to_mem

axi_to_mem_interleaved

AXI4+ATOP to SRAM memory slave. Allows for parallel read and write transactions.

axi_to_mem_interleaved_intf

AXI4+ATOP interface wrapper for axi_to_mem_interleaved

axi_to_mem_split

AXI4+ATOP to memory-protocol interconnect. Completely separates the read and write channel to

axi_to_mem_split_intf

AXI4+ATOP interface wrapper for axi_to_mem_split

axi_xbar

axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports.

axi_xbar_intf
axi_xp

AXI Crosspoint (XP) with homomorphous slave and master ports.

axi_xp_intf
axi_zero_mem

AXI4+ATOP slave module which translates AXI bursts into a memory stream

Parameters

AXI_ADDR_WIDTH: int unsigned

AXI_DATA_WIDTH: int unsigned

AXI_ID_WIDTH: int unsigned

AXI_USER_WIDTH: int unsigned

AXI_STRB_WIDTH: int unsigned

AXI_ADDR_WIDTH: int unsigned

AXI_DATA_WIDTH: int unsigned

AXI_ID_WIDTH: int unsigned

AXI_USER_WIDTH: int unsigned

AXI_STRB_WIDTH: int unsigned

AXI_ADDR_WIDTH: int unsigned

AXI_DATA_WIDTH: int unsigned

AXI_ID_WIDTH: int unsigned

AXI_USER_WIDTH: int unsigned

BUFFER_WIDTH: int unsigned

AXI_STRB_WIDTH: int unsigned

AXI_ADDR_WIDTH: int unsigned

AXI_DATA_WIDTH: int unsigned

AXI_ID_WIDTH: int unsigned

AXI_USER_WIDTH: int unsigned

LOG_DEPTH: int unsigned

AXI_STRB_WIDTH: int unsigned

AXI_ADDR_WIDTH: int unsigned

AXI_DATA_WIDTH: int unsigned

AXI_STRB_WIDTH: int unsigned

AXI_ADDR_WIDTH: int unsigned

AXI_DATA_WIDTH: int unsigned

AXI_STRB_WIDTH:

AXI_ADDR_WIDTH: int unsigned

AXI_DATA_WIDTH: int unsigned

LOG_DEPTH: int unsigned

AXI_STRB_WIDTH: int unsigned

Ports

clk_i: input logic

clk_i: input logic

Types

id_t
addr_t
data_t
strb_t
user_t
id_t
addr_t
data_t
strb_t
user_t
id_t
addr_t
data_t
strb_t
user_t
buffer_t
id_t
addr_t
data_t
strb_t
user_t
aw_chan_t
w_chan_t
b_chan_t
ar_chan_t
r_chan_t
addr_t
data_t
strb_t
addr_t
data_t
strb_t
addr_t
data_t
strb_t
aw_chan_t
w_chan_t
b_chan_t
ar_chan_t
r_chan_t

Signals

aw_id: id_t

aw_addr: addr_t

aw_user: user_t

w_data: data_t

w_strb: strb_t

w_user: user_t

b_id: id_t

b_user: user_t

ar_id: id_t

ar_addr: addr_t

ar_user: user_t

r_id: id_t

r_data: data_t

r_user: user_t

aw_id: id_t

aw_addr: addr_t

aw_user: user_t

w_data: data_t

w_strb: strb_t

w_user: user_t

b_id: id_t

b_user: user_t

ar_id: id_t

ar_addr: addr_t

ar_user: user_t

r_id: id_t

r_data: data_t

r_user: user_t

aw_id: id_t

aw_addr: addr_t

aw_user: user_t

aw_writetoken: buffer_t

aw_readpointer: buffer_t

w_data: data_t

w_strb: strb_t

w_user: user_t

w_writetoken: buffer_t

w_readpointer: buffer_t

b_id: id_t

b_user: user_t

b_writetoken: buffer_t

b_readpointer: buffer_t

ar_id: id_t

ar_addr: addr_t

ar_user: user_t

ar_writetoken: buffer_t

ar_readpointer: buffer_t

r_id: id_t

r_data: data_t

r_user: user_t

r_writetoken: buffer_t

r_readpointer: buffer_t

aw_addr: addr_t

w_data: data_t

w_strb: strb_t

ar_addr: addr_t

r_data: data_t

aw_addr: addr_t

w_data: data_t

w_strb: strb_t

ar_addr: addr_t

r_data: data_t