Module axi_bus_compare
Synthesizable test module comparing two AXI channels of the same type
This module is meant to be used in FPGA-based verification.
Parameters
AxiIdWidth: int unsigned
ID width of the AXI4+ATOP interface
FifoDepth: int unsigned
FIFO depth
UseSize: bit
Consider size field in comparison
DataWidth: int unsigned
Data width of the AXI4+ATOP interface
axi_aw_chan_t: type
AW channel type of the AXI4+ATOP interface
axi_w_chan_t: type
W channel type of the AXI4+ATOP interface
axi_b_chan_t: type
B channel type of the AXI4+ATOP interface
axi_ar_chan_t: type
AR channel type of the AXI4+ATOP interface
axi_r_chan_t: type
R channel type of the AXI4+ATOP interface
axi_req_t: type
Request struct type of the AXI4+ATOP slave port
axi_rsp_t: type
Response struct type of the AXI4+ATOP slave port
id_t: type
ID type (do not overwrite)
Ports
clk_i: input logic
Clock
rst_ni: input logic
Asynchronous reset, active low
testmode_i: input logic
Testmode
axi_a_req_i: input axi_req_t
AXI4+ATOP A channel request in
axi_a_rsp_o: output axi_rsp_t
AXI4+ATOP A channel response out
axi_a_req_o: output axi_req_t
AXI4+ATOP A channel request out
axi_a_rsp_i: input axi_rsp_t
AXI4+ATOP A channel response in
axi_b_req_i: input axi_req_t
AXI4+ATOP B channel request in
axi_b_rsp_o: output axi_rsp_t
AXI4+ATOP B channel response out
axi_b_req_o: output axi_req_t
AXI4+ATOP B channel request out
axi_b_rsp_i: input axi_rsp_t
AXI4+ATOP B channel response in
aw_mismatch_o: output id_t
AW mismatch
w_mismatch_o: output logic
W mismatch
b_mismatch_o: output id_t
B mismatch
ar_mismatch_o: output id_t
AR mismatch
r_mismatch_o: output id_t
R mismatch
mismatch_o: output logic
General mismatch
busy_o: output logic
Unit is busy