Module axi_cdc
A clock domain crossing on an AXI interface.
For each of the five AXI channels, this module instantiates a CDC FIFO, whose push and pop
ports are in separate clock domains. IMPORTANT: For each AXI channel, you MUST properly
constrain three paths through the FIFO; see the header of cdc_fifo_gray for instructions.
Parameters
aw_chan_t: type
w_chan_t: type
b_chan_t: type
ar_chan_t: type
r_chan_t: type
axi_req_t: type
axi_resp_t: type
LogDepth: int unsigned
Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
SyncStages: int unsigned
Number of synchronization registers to insert on the async pointers