Module axi_cdc_src

Source-clock-domain half of the AXI CDC crossing.

For each of the five AXI channels, this module instantiates the source or destination half of

a CDC FIFO. IMPORTANT: For each AXI channel, you MUST properly constrain three paths through

the FIFO; see the header of cdc_fifo_gray for instructions.

Parameters

LogDepth: int unsigned

Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.

SyncStages: int unsigned

Number of synchronization registers to insert on the async pointers

aw_chan_t: type

w_chan_t: type

b_chan_t: type

ar_chan_t: type

r_chan_t: type

axi_req_t: type

axi_resp_t: type

Ports

src_clk_i: input logic

src_rst_ni: input logic

src_req_i: input axi_req_t

src_resp_o: output axi_resp_t

async_data_master_aw_data_o: output aw_chan_t [2**LogDepth-1:0]

async_data_master_aw_wptr_o: output logic [LogDepth:0]

async_data_master_aw_rptr_i: input logic [LogDepth:0]

async_data_master_w_data_o: output w_chan_t [2**LogDepth-1:0]

async_data_master_w_wptr_o: output logic [LogDepth:0]

async_data_master_w_rptr_i: input logic [LogDepth:0]

async_data_master_b_data_i: input b_chan_t [2**LogDepth-1:0]

async_data_master_b_wptr_i: input logic [LogDepth:0]

async_data_master_b_rptr_o: output logic [LogDepth:0]

async_data_master_ar_data_o: output ar_chan_t [2**LogDepth-1:0]

async_data_master_ar_wptr_o: output logic [LogDepth:0]

async_data_master_ar_rptr_i: input logic [LogDepth:0]

async_data_master_r_data_i: input r_chan_t [2**LogDepth-1:0]

async_data_master_r_wptr_i: input logic [LogDepth:0]

async_data_master_r_rptr_o: output logic [LogDepth:0]