Module axi_delayer

Synthesizable module that (randomly) delays AXI channels.

Parameters

aw_chan_t: type

w_chan_t: type

b_chan_t: type

ar_chan_t: type

r_chan_t: type

axi_req_t: type

axi_resp_t: type

StallRandomInput: bit

StallRandomOutput: bit

FixedDelayInput: int unsigned

FixedDelayOutput: int unsigned

Ports

clk_i: input logic

rst_ni: input logic

slv_req_i: input axi_req_t

slv_resp_o: output axi_resp_t

mst_req_o: output axi_req_t

mst_resp_i: input axi_resp_t