Module axi_delayer_intf
Parameters
AXI_ID_WIDTH: int unsigned
AXI_ADDR_WIDTH: int unsigned
AXI_DATA_WIDTH: int unsigned
AXI_USER_WIDTH: int unsigned
STALL_RANDOM_INPUT: bit
STALL_RANDOM_OUTPUT: bit
FIXED_DELAY_INPUT: int unsigned
FIXED_DELAY_OUTPUT: int unsigned
Ports
clk_i: input logic
rst_ni: input logic
slv: AXI_BUS.Slave
mst: AXI_BUS.Master
Types
| id_t | |
| addr_t | |
| data_t | |
| strb_t | |
| user_t | |
| aw_chan_t | |
| w_chan_t | |
| b_chan_t | |
| ar_chan_t | |
| r_chan_t | |
| axi_req_t | |
| axi_resp_t |