Module axi_demux

Demultiplex one AXI4+ATOP slave port to multiple AXI4+ATOP master ports.

The AW and AR slave channels each have a select input to determine to which master port the

current request is sent. The select can, for example, be driven by an address decoding module

to map address ranges to different AXI slaves.

Design overview

Block diagram

Beats on the W channel are routed by demultiplexer according to the selection for the

corresponding AW beat. This relies on the AXI property that W bursts must be sent in the same

order as AW beats and beats from different W bursts may not be interleaved.

Beats on the B and R channel are multiplexed from the master ports to the slave port with

a round-robin arbitration tree.

Parameters

AxiIdWidth: int unsigned

AtopSupport: bit

aw_chan_t: type

w_chan_t: type

b_chan_t: type

ar_chan_t: type

r_chan_t: type

axi_req_t: type

axi_resp_t: type

NoMstPorts: int unsigned

MaxTrans: int unsigned

AxiLookBits: int unsigned

UniqueIds: bit

SpillAw: bit

SpillW: bit

SpillB: bit

SpillAr: bit

SpillR: bit

SelectWidth: int unsigned

select_t: type

Ports

clk_i: input logic

rst_ni: input logic

test_i: input logic

slv_req_i: input axi_req_t

slv_aw_select_i: input select_t

slv_ar_select_i: input select_t

slv_resp_o: output axi_resp_t

mst_reqs_o: output axi_req_t [NoMstPorts-1:0]

mst_resps_i: input axi_resp_t [NoMstPorts-1:0]

Signals

slv_req_cut: axi_req_t

slv_resp_cut: axi_resp_t

slv_aw_select: select_t

slv_ar_select: select_t