Module axi_dw_upsizer

Parameters

`AxiMaxReads: int unsigned`

`AxiSlvPortDataWidth: int unsigned`

`AxiMstPortDataWidth: int unsigned`

`AxiAddrWidth: int unsigned`

`AxiIdWidth: int unsigned`

`aw_chan_t: type`

`mst_w_chan_t: type`

`slv_w_chan_t: type`

`b_chan_t: type`

`ar_chan_t: type`

`mst_r_chan_t: type`

`slv_r_chan_t: type`

`axi_mst_req_t: type`

`axi_mst_resp_t: type`

`axi_slv_req_t: type`

`axi_slv_resp_t: type`

`TranIdWidth:`

`AxiSlvPortStrbWidth:`

`AxiMstPortStrbWidth:`

`AxiSlvPortMaxSize:`

`AxiMstPortMaxSize:`

Ports

`clk_i: input logic`

`rst_ni: input logic`

`slv_req_i: input axi_slv_req_t`

`slv_resp_o: output axi_slv_resp_t`

`mst_req_o: output axi_mst_req_t`

`mst_resp_i: input axi_mst_resp_t`

Types

tran_id_t
mst_data_t
slv_data_t
addr_t
id_t
burst_len_t
r_state_e
w_req_t
r_req_t
w_state_e

Signals

`mst_req: axi_mst_req_t`

`mst_resp: axi_mst_resp_t`

`arb_slv_ar_id: id_t`

`mst_req_idx: tran_id_t`

`axi_err_req: axi_mst_req_t`

`axi_err_resp: axi_mst_resp_t`

`w_req_d: w_req_t`

`w_req_q: w_req_t`

`idx_ar_upsizer: tran_id_t`

`idx_idle_upsizer: tran_id_t`

`idx_id_clash_upsizer: tran_id_t`

`idx_r_upsizer: tran_id_t`

`r_state_d: r_state_e`

`r_state_q: r_state_e`

`r_req_d: r_req_t`

`r_req_q: r_req_t`

`r_data: slv_data_t`

`w_state_d: w_state_e`

`w_state_q: w_state_e`

`w_data: mst_data_t`