Module axi_err_slv

Parameters

`AxiIdWidth: int unsigned`

`axi_req_t: type`

`axi_resp_t: type`

`Resp: axi_pkg::resp_t`

`RespWidth: int unsigned`

`RespData: logic [RespWidth-1:0]`

`ATOPs: bit`

`MaxTrans: int unsigned`

Ports

`clk_i: input logic`

`rst_ni: input logic`

`test_i: input logic`

`slv_req_i: input axi_req_t`

`slv_resp_o: output axi_resp_t`

Types

id_t
r_data_t

Signals

`err_req: axi_req_t`

`err_resp: axi_resp_t`

`w_fifo_data: id_t`

`b_fifo_data: id_t`

`r_fifo_inp: r_data_t`

`r_fifo_data: r_data_t`