Module axi_fifo_delay_dyn

Delay and buffer an AXI bus

Parameters

`aw_chan_t: type`

`w_chan_t: type`

`b_chan_t: type`

`ar_chan_t: type`

`r_chan_t: type`

`axi_req_t: type`

`axi_resp_t: type`

`DepthAR: int unsigned`

`DepthAW: int unsigned`

`DepthR: int unsigned`

`DepthW: int unsigned`

`DepthB: int unsigned`

`MaxDelay: int unsigned`

`DelayWidth: int unsigned`

Ports

`clk_i: input logic`

`rst_ni: input logic`

`aw_delay_i: input logic [DelayWidth-1:0]`

`w_delay_i: input logic [DelayWidth-1:0]`

`b_delay_i: input logic [DelayWidth-1:0]`

`ar_delay_i: input logic [DelayWidth-1:0]`

`r_delay_i: input logic [DelayWidth-1:0]`

`slv_req_i: input axi_req_t`

`slv_resp_o: output axi_resp_t`

`mst_req_o: output axi_req_t`

`mst_resp_i: input axi_resp_t`