Module axi_fifo_delay_dyn_intf
Delay and buffer an AXI bus interface wrapper
Parameters
AXI_ID_WIDTH: int unsigned
AXI_ADDR_WIDTH: int unsigned
AXI_DATA_WIDTH: int unsigned
AXI_USER_WIDTH: int unsigned
DEPTH_AR: int unsigned
DEPTH_AW: int unsigned
DEPTH_R: int unsigned
DEPTH_W: int unsigned
DEPTH_B: int unsigned
MAX_DELAY: int unsigned
DELAY_WIDTH: int unsigned
Ports
clk_i: input logic
rst_ni: input logic
aw_delay_i: input logic [MAX_DELAY-1:0]
w_delay_i: input logic [MAX_DELAY-1:0]
b_delay_i: input logic [MAX_DELAY-1:0]
ar_delay_i: input logic [MAX_DELAY-1:0]
r_delay_i: input logic [MAX_DELAY-1:0]
slv: AXI_BUS.Slave
mst: AXI_BUS.Master
Types
| id_t | |
| addr_t | |
| data_t | |
| strb_t | |
| user_t | |
| aw_chan_t | |
| w_chan_t | |
| b_chan_t | |
| ar_chan_t | |
| r_chan_t | |
| axi_req_t | |
| axi_resp_t |