Module axi_fifo_intf
Parameters
ADDR_WIDTH: int unsigned
DATA_WIDTH: int unsigned
ID_WIDTH: int unsigned
USER_WIDTH: int unsigned
DEPTH: int unsigned
FALL_THROUGH: int unsigned
Ports
clk_i: input logic
rst_ni: input logic
test_i: input logic
slv: AXI_BUS.Slave
mst: AXI_BUS.Master
Types
| id_t | |
| addr_t | |
| data_t | |
| strb_t | |
| user_t | |
| aw_chan_t | |
| w_chan_t | |
| b_chan_t | |
| ar_chan_t | |
| r_chan_t | |
| axi_req_t | |
| axi_resp_t |