Module axi_from_mem
Protocol adapter which translates memory requests to the AXI4 protocol.
This module acts like an SRAM and makes AXI4 requests downstream.
Supports multiple outstanding requests and will have responses for reads and writes.
Response latency is not fixed and for sure not 1 and depends on the AXI4 memory system.
The mem_rsp_valid_o can have multiple cycles of latency from the corresponding mem_gnt_o.
Parameters
MemAddrWidth: int unsigned
Memory request address width.
AxiAddrWidth: int unsigned
AXI4-Lite address width.
DataWidth: int unsigned
Data width in bit of the memory request data and the Axi4-Lite data channels.
MaxRequests: int unsigned
How many requests can be in flight at the same time. (Depth of the response mux FIFO).
AxiProt: axi_pkg::prot_t
Protection signal the module should emit on the AXI4 transactions.
axi_req_t: type
AXI4 request struct definition.
axi_rsp_t: type
AXI4 response struct definition.
Ports
clk_i: input logic
Clock input, positive edge triggered.
rst_ni: input logic
Asynchronous reset, active low.
mem_req_i: input logic
Memory slave port, request is active.
mem_addr_i: input logic [MemAddrWidth-1:0]
Memory slave port, request address.
Byte address, will be extended or truncated to match AxiAddrWidth.
mem_we_i: input logic
Memory slave port, request is a write.
0: Read request.
1: Write request.
mem_wdata_i: input logic [DataWidth-1:0]
Memory salve port, write data for request.
mem_be_i: input logic [DataWidth/8-1:0]
Memory slave port, write byte enable for request.
Active high.
mem_gnt_o: output logic
Memory request is granted.
mem_rsp_valid_o: output logic
Memory slave port, response is valid. For each request, regardless if read or write,
this will be active once for one cycle.
mem_rsp_rdata_o: output logic [DataWidth-1:0]
Memory slave port, response read data. This is forwarded directly from the AXI4-Lite
R channel. Only valid for responses generated by a read request.
mem_rsp_error_o: output logic
Memory request encountered an error. This is forwarded from the AXI4-Lite error response.
slv_aw_cache_i: input axi_pkg::cache_t
AXI4 master port, slave aw cache signal
slv_ar_cache_i: input axi_pkg::cache_t
AXI4 master port, slave ar cache signal
axi_req_o: output axi_req_t
AXI4 master port, request output.
axi_rsp_i: input axi_rsp_t
AXI4 master port, response input.
Types
| axi_lite_aw_chan_t | |
| axi_lite_w_chan_t | |
| axi_lite_b_chan_t | |
| axi_lite_ar_chan_t | |
| axi_lite_r_chan_t | |
| axi_lite_req_t | |
| axi_lite_resp_t |