NoBus: int unsignedAxiIdWidthSlvPort: int unsignedAxiIdWidthMstPort: int unsignedslv_aw_chan_t: typeslv_w_chan_t: typeslv_b_chan_t: typeslv_ar_chan_t: typeslv_r_chan_t: typemst_aw_chan_t: typemst_w_chan_t: typemst_b_chan_t: typemst_ar_chan_t: typemst_r_chan_t: typePreIdWidth: int unsignedpre_id_i: input logic [PreIdWidth-1:0]slv_aw_chans_i: input slv_aw_chan_t [NoBus-1:0]slv_aw_valids_i: input logic [NoBus-1:0]slv_aw_readies_o: output logic [NoBus-1:0]slv_w_chans_i: input slv_w_chan_t [NoBus-1:0]slv_w_valids_i: input logic [NoBus-1:0]slv_w_readies_o: output logic [NoBus-1:0]slv_b_chans_o: output slv_b_chan_t [NoBus-1:0]slv_b_valids_o: output logic [NoBus-1:0]slv_b_readies_i: input logic [NoBus-1:0]slv_ar_chans_i: input slv_ar_chan_t [NoBus-1:0]slv_ar_valids_i: input logic [NoBus-1:0]slv_ar_readies_o: output logic [NoBus-1:0]slv_r_chans_o: output slv_r_chan_t [NoBus-1:0]slv_r_valids_o: output logic [NoBus-1:0]slv_r_readies_i: input logic [NoBus-1:0]mst_aw_chans_o: output mst_aw_chan_t [NoBus-1:0]mst_aw_valids_o: output logic [NoBus-1:0]mst_aw_readies_i: input logic [NoBus-1:0]mst_w_chans_o: output mst_w_chan_t [NoBus-1:0]mst_w_valids_o: output logic [NoBus-1:0]mst_w_readies_i: input logic [NoBus-1:0]mst_b_chans_i: input mst_b_chan_t [NoBus-1:0]mst_b_valids_i: input logic [NoBus-1:0]mst_b_readies_o: output logic [NoBus-1:0]mst_ar_chans_o: output mst_ar_chan_t [NoBus-1:0]mst_ar_valids_o: output logic [NoBus-1:0]mst_ar_readies_i: input logic [NoBus-1:0]mst_r_chans_i: input mst_r_chan_t [NoBus-1:0]mst_r_valids_i: input logic [NoBus-1:0]mst_r_readies_o: output logic [NoBus-1:0]