Module axi_interleaved_xbar
Interleaved version of the crossbar. This module is experimental; use at your own risk.
Parameters
Cfg: axi_pkg::xbar_cfg_t
ATOPs: bit
Connectivity: bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0]
slv_aw_chan_t: type
mst_aw_chan_t: type
w_chan_t: type
slv_b_chan_t: type
mst_b_chan_t: type
slv_ar_chan_t: type
mst_ar_chan_t: type
slv_r_chan_t: type
mst_r_chan_t: type
slv_req_t: type
slv_resp_t: type
mst_req_t: type
mst_resp_t: type
rule_t: type
MstPortsIdxWidth: int unsigned
cfg_NoMstPorts: int unsigned
BankSelLow: int unsigned
BankSelHigh: int unsigned
Ports
clk_i: input logic
rst_ni: input logic
test_i: input logic
slv_ports_req_i: input slv_req_t [Cfg.NoSlvPorts-1:0]
slv_ports_resp_o: output slv_resp_t [Cfg.NoSlvPorts-1:0]
mst_ports_req_o: output mst_req_t [Cfg.NoMstPorts-1:0]
mst_ports_resp_i: input mst_resp_t [Cfg.NoMstPorts-1:0]
addr_map_i: input rule_t [Cfg.NoAddrRules-1:0]
interleaved_mode_ena_i: input logic
en_default_mst_port_i: input logic [Cfg.NoSlvPorts-1:0]
default_mst_port_i: input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0]
Types
| addr_t | |
| mst_port_idx_t |