Module axi_interleaved_xbar_intf

Parameters

Cfg: axi_pkg::xbar_cfg_t

AXI_USER_WIDTH: int unsigned

ATOPS: bit

CONNECTIVITY: bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0]

rule_t: type

AxiIdWidthMstPorts: int unsigned

Ports

clk_i: input logic

rst_ni: input logic

test_i: input logic

slv_ports: AXI_BUS.Slave

mst_ports: AXI_BUS.Master

addr_map_i: input rule_t [Cfg.NoAddrRules-1:0]

en_default_mst_port_i: input logic [Cfg.NoSlvPorts-1:0]

interleaved_mode_ena_i: input logic

default_mst_port_i: input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0]

Types