Module axi_inval_filter

Parameters

`MaxTxns: int unsigned`

`AddrWidth: int unsigned`

`L1LineWidth: int unsigned`

`aw_chan_t: type`

`req_t: type`

`resp_t: type`

Ports

`clk_i: input logic`

`rst_ni: input logic`

`en_i: input logic`

`slv_req_i: input req_t`

`slv_resp_o: output resp_t`

`mst_req_o: output req_t`

`mst_resp_i: input resp_t`

`inval_addr_o: output logic [AddrWidth-1:0]`

`inval_valid_o: output logic`

`inval_ready_i: input logic`

Signals

`aw_fifo_data: aw_chan_t`