Module axi_lite_cdc_dst_intf
Parameters
AXI_ADDR_WIDTH: int unsigned
AXI_DATA_WIDTH: int unsigned
LOG_DEPTH: int unsigned
Depth of the FIFO crossing the clock domain, given as 2**LOG_DEPTH.
SYNC_STAGES: int unsigned
Number of synchronization registers to insert on the async pointers
Ports
src: AXI_LITE_ASYNC_GRAY.Slave
dst_clk_i: input logic
dst_rst_ni: input logic
dst: AXI_LITE.Master
Types
| addr_t | |
| data_t | |
| strb_t | |
| aw_chan_t | |
| w_chan_t | |
| b_chan_t | |
| ar_chan_t | |
| r_chan_t | |
| req_t | |
| resp_t |