Module axi_lite_cut_intf
Parameters
BYPASS: bit
ADDR_WIDTH: int unsigned
The address width.
DATA_WIDTH: int unsigned
The data width.
Ports
clk_i: input logic
rst_ni: input logic
in: AXI_LITE.Slave
out: AXI_LITE.Master
Types
| addr_t | |
| data_t | |
| strb_t | |
| aw_chan_t | |
| w_chan_t | |
| b_chan_t | |
| ar_chan_t | |
| r_chan_t | |
| axi_req_t | |
| axi_resp_t |