Module axi_lite_demux

Parameters

`aw_chan_t: type`

`w_chan_t: type`

`b_chan_t: type`

`ar_chan_t: type`

`r_chan_t: type`

`axi_req_t: type`

`axi_resp_t: type`

`NoMstPorts: int unsigned`

`MaxTrans: int unsigned`

`FallThrough: bit`

`SpillAw: bit`

`SpillW: bit`

`SpillB: bit`

`SpillAr: bit`

`SpillR: bit`

`select_t: type`

Ports

`clk_i: input logic`

`rst_ni: input logic`

`test_i: input logic`

`slv_req_i: input axi_req_t`

`slv_aw_select_i: input select_t`

`slv_ar_select_i: input select_t`

`slv_resp_o: output axi_resp_t`

`mst_reqs_o: output axi_req_t [NoMstPorts-1:0]`

`mst_resps_i: input axi_resp_t [NoMstPorts-1:0]`

Types

aw_chan_select_t
ar_chan_select_t
aw_chan_select_flat_t
ar_chan_select_flat_t

Signals

`slv_aw_chan: aw_chan_select_t`

`slv_w_chan: w_chan_t`

`w_select: select_t`

`slv_b_chan: b_chan_t`

`b_select: select_t`

`slv_ar_chan: ar_chan_select_t`

`slv_r_chan: r_chan_t`

`r_select: select_t`

`slv_aw_chan_select_in_flat: aw_chan_select_flat_t`

`slv_aw_chan_select_out_flat: aw_chan_select_flat_t`

`slv_ar_chan_select_in_flat: ar_chan_select_flat_t`

`slv_ar_chan_select_out_flat: ar_chan_select_flat_t`