Module axi_lite_dw_converter
Parameters
AxiAddrWidth: int unsigned
AXI4-Lite address width of the ports.
AxiSlvPortDataWidth: int unsigned
AXI4-Lite data width of the slave port.
AxiMstPortDataWidth: int unsigned
AXI4-Lite data width of the master port.
axi_lite_aw_t: type
AXI4-Lite AW channel struct type. This is for both ports the same.
axi_lite_slv_w_t: type
AXI4-Lite W channel struct type of the slave port.
axi_lite_mst_w_t: type
AXI4-Lite W channel struct type of the master port.
axi_lite_b_t: type
AXI4-Lite B channel struct type. This is for both ports.
axi_lite_ar_t: type
AXI4-Lite AR channel struct type. This is for both ports.
axi_lite_slv_r_t: type
AXI4-Lite R channel struct type of the slave port.
axi_lite_mst_r_t: type
AXI4-Lite R channel struct type of the master port.
axi_lite_slv_req_t: type
AXI4-Lite request struct of the slave port.
axi_lite_slv_res_t: type
AXI4-Lite response struct of the slave port.
axi_lite_mst_req_t: type
AXI4-Lite request struct of the master port.
axi_lite_mst_res_t: type
AXI4-Lite response struct of the master port.
AxiSlvPortStrbWidth: int unsigned
AxiMstPortStrbWidth: int unsigned
DownsizeFactor: int unsigned
SelWidth: int unsigned
SelOffset: int unsigned
UpsizeFactor: int unsigned
SelOffset: int unsigned
SelWidth: int unsigned
Ports
clk_i: input logic
Clock, positive edge triggered.
rst_ni: input logic
Asynchrounous reset, active low.
slv_req_i: input axi_lite_slv_req_t
Salve port, AXI4-Lite request.
slv_res_o: output axi_lite_slv_res_t
Salve port, AXI4-Lite response.
mst_req_o: output axi_lite_mst_req_t
Master port, AXI4-Lite request.
mst_res_i: input axi_lite_mst_res_t
Master port, AXI4-Lite response.
Types
| addr_t | |
| sel_t | |
| sel_t |