Module axi_lite_dw_converter_intf
Parameters
AXI_ADDR_WIDTH: int unsigned
AXI4-Lite address width of the ports.
AXI_SLV_PORT_DATA_WIDTH: int unsigned
AXI4-Lite data width of the slave port.
AXI_MST_PORT_DATA_WIDTH: int unsigned
AXI4-Lite data width of the master port.
AxiStrbWidthSlv: int unsigned
AxiStrbWidthMst: int unsigned
Ports
clk_i: input logic
Clock, positive edge triggered.
rst_ni: input logic
Asynchrounous reset, active low.
slv: AXI_LITE.Slave
Slave port interface.
mst: AXI_LITE.Master
Master port interface.