Module axi_lite_from_mem
Protocol adapter which translates memory requests to the AXI4-Lite protocol.
This module acts like an SRAM and makes AXI4-Lite requests downstream.
Supports multiple outstanding requests and will have responses for reads and writes.
Response latency is not fixed and for sure not 1 and depends on the AXI4-Lite memory system.
The mem_rsp_valid_o can have multiple cycles of latency from the corresponding mem_gnt_o.
(Was called mem_to_axi_lite - originating from https://github.com/pulp-platform/snitch)
Parameters
MemAddrWidth: int unsigned
Memory request address width.
AxiAddrWidth: int unsigned
AXI4-Lite address width.
DataWidth: int unsigned
Data width in bit of the memory request data and the Axi4-Lite data channels.
MaxRequests: int unsigned
How many requests can be in flight at the same time. (Depth of the response mux FIFO).
AxiProt: axi_pkg::prot_t
Protection signal the module should emit on the AXI4-Lite transactions.
axi_req_t: type
AXI4-Lite request struct definition.
axi_rsp_t: type
AXI4-Lite response struct definition.
mem_addr_t: type
Dependent parameter do not overwrite!
Memory address type, derived from MemAddrWidth.
axi_addr_t: type
Dependent parameter do not overwrite!
AXI4-Lite address type, derived from AxiAddrWidth.
data_t: type
Dependent parameter do not overwrite!
Data type for read and write data, derived from DataWidth.
This is the same for the memory request side and the AXI4-Lite W and R channels.
strb_t: type
Dependent parameter do not overwrite!
Byte enable / AXI4-Lite strobe type, derived from DataWidth.
Ports
clk_i: input logic
Clock input, positive edge triggered.
rst_ni: input logic
Asynchronous reset, active low.
mem_req_i: input logic
Memory slave port, request is active.
mem_addr_i: input mem_addr_t
Memory slave port, request address.
Byte address, will be extended or truncated to match AxiAddrWidth.
mem_we_i: input logic
Memory slave port, request is a write.
0: Read request.
1: Write request.
mem_wdata_i: input data_t
Memory salve port, write data for request.
mem_be_i: input strb_t
Memory slave port, write byte enable for request.
Active high.
mem_gnt_o: output logic
Memory request is granted.
mem_rsp_valid_o: output logic
Memory slave port, response is valid. For each request, regardless if read or write,
this will be active once for one cycle.
mem_rsp_rdata_o: output data_t
Memory slave port, response read data. This is forwarded directly from the AXI4-Lite
R channel. Only valid for responses generated by a read request.
mem_rsp_error_o: output logic
Memory request encountered an error. This is forwarded from the AXI4-Lite error response.
axi_req_o: output axi_req_t
AXI4-Lite master port, request output.
axi_rsp_i: input axi_rsp_t
AXI4-Lite master port, response input.