Module axi_lite_regs

AXI4-Lite registers with optional read-only and protection features.

This module contains a parametrizable number of bytes in flip-flops (FFs) and makes them

accessible on two interfaces:

• as memory-mapped AXI4-Lite slave (ports axi_req_i and axi_resp_o), and

• as wires to directly attach other hardware logic (ports reg_d_i, reg_load_i, reg_q_o,

  wr_active_o, rd_active_o).

Address Map

The address range covered by this module is defined by RegNumBytes. The base address of this

module must be aligned to RegNumBytes. The first byte is accessible at offset 0, the last

byte is accessible at offset RegNumBytes-1. The slice [$clog2(RegNumBytes)-1:0] of a given

address is used to decode the accessed byte within this module. Address bits outside that slice

are ignored. Accesses to addresses within the slice but with an offset above the last byte are

responded with SLVERR.

Read-Only Bytes

Any set of bytes can be configured as read-only by setting the AxiReadOnly parameter

accordingly. A read-only byte cannot be written via the AXI interface, but it can be changed

from the logic interface.

When one or multiple bytes in a write transaction are read-only, they are not modified. A write

transaction is responded with OKAY if it wrote at least one byte. Write transactions / that

have wstrb set only for read-only bytes are responded with SLVERR.

This read-only mechanism can be used to expose constants (lookup-table data) as follows.

Exposing Constants

To make a byte with constant value (e.g., implemented as LUT instead of FF after synthesis)

readable from the AXI4-Lite port:

• Make the byte read-only from the AXI4-Lite port by setting its AxiReadOnly bit to 1.

• Disable loading the byte from logic by driving its reg_load_i bit to 0.

• Define the value of the byte by setting its RegRstVal entry.

Protection

This module can be configured to only allow privileged and/or secure accesses (see A4.7

of the AXI4 specification) by setting the PrivProtOnly and/or SecuProtOnly parameter,

respectively.

The size of the register field in bytes.

Address width of the AXI4-Lite port.

The minimum value of this parameter is $clog2(RegNumBytes).

Data width of the AXI4-Lite port.

Only allow privileged accesses on the AXI4-Lite port.

If this parameter is set to 1, this module only allows reads and writes that have the

AxProt[0] bit set. If a transaction does not have the AxProt[0] bit set, this module

replies with SLVERR and does not read or write register data.

Only allow secure accesses on the AXI4-Lite port.

If this parameter is set to 1, this module only allows reads and writes that have the

AxProt[1] bit set. If a transaction does not have the AxProt[1] bit set, this module

replies with SLVERR and does not read or write register data.

Define individual bytes as read-only from the AXI4-Lite port.

This parameter is an array with one bit for each byte. If that bit is 0, the byte can be

read and written on the AXI4-Lite port; if that bit is 1, the byte can only be read on the

AXI4-Lite port.

Constant (=do not overwrite!); type of a byte is 8 bit.

Reset value for the whole register array.

This parameter is an array with one byte value for each byte. At reset, each byte is

assigned its value from this array.

Request struct of the AXI4-Lite port.

Response struct of the AXI4-Lite port.

Rising-edge clock of all ports

Asynchronous reset, active low

AXI4-Lite slave request

AXI4-Lite slave response

Signals that a byte is being written from the AXI4-Lite port in the current clock cycle. This

signal is asserted regardless of the value of AxiReadOnly and can therefore be used by

surrounding logic to react to write-on-read-only-byte errors.

Signals that a byte is being read from the AXI4-Lite port in the current clock cycle.

Input value of each byte. If reg_load_i is 1 for a byte in the current clock cycle, the

byte register in this module is set to the value of the byte in reg_d_i at the next clock

edge.

Load enable of each byte.

If reg_load_i is 1 for a byte defined as non-read-only in a clock cycle, an AXI4-Lite

write transaction is stalled when it tries to write the same byte. That is, a write

transaction is stalled if all of the following conditions are true for the byte at index i:

• AxiReadOnly[i] is 0,

• reg_load_i[i] is 1,

• the bit in axi_req_i.w.strb that affects the byte is 1.

If unused, set this input to '0.

The registered value of each byte.