Module axi_sim_mem
Infinite (Simulation-Only) Memory with AXI Slave Port
The memory array is named mem, and it is not initialized or reset. This makes it possible to
load the memory of this module in simulation with an external $readmem* command, e.g.,
axi_sim_mem #( ... ) i_sim_mem ( ... );
initial begin
$readmemh("file_with_memory_addrs_and_data.mem", i_sim_mem.mem);
$readmemh("file_with_memory_addrs_and_read_errors.mem", i_sim_mem.rerr);
$readmemh("file_with_memory_addrs_and_write_errors.mem", i_sim_mem.werr);
end
mem is addressed (or indexed) byte-wise with AddrWidth-wide addresses.
This module does not support atomic operations (ATOPs).
Parameters
AddrWidth: int unsigned
AXI Address Width
DataWidth: int unsigned
AXI Data Width
IdWidth: int unsigned
AXI ID Width
UserWidth: int unsigned
AXI User Width.
NumPorts: int unsigned
Number of request ports
axi_req_t: type
AXI4 request struct definition
axi_rsp_t: type
AXI4 response struct definition
WarnUninitialized: bit
Warn on accesses to uninitialized bytes
UninitializedData:
Default value for uninitialized memory (undefined, zeros, ones, random)
ClearErrOnAccess: bit
Clear error on access
ApplDelay: time
Application delay (measured after rising clock edge)
AcqDelay: time
Acquisition delay (measured after rising clock edge)
StrbWidth: int unsigned
Ports
clk_i: input logic
Rising-edge clock
rst_ni: input logic
Active-low reset
axi_req_i: input axi_req_t [NumPorts-1:0]
AXI4 request struct
axi_rsp_o: output axi_rsp_t [NumPorts-1:0]
AXI4 response struct
mon_w_valid_o: output logic [NumPorts-1:0]
Memory monitor write valid. All mon_w_* outputs are only valid if this signal is high.
A write to the memory is visible on the mon_w_* outputs in the clock cycle after it has
happened.
mon_w_addr_o: output logic [NumPorts-1:0][AddrWidth-1:0]
Memory monitor write address
mon_w_data_o: output logic [NumPorts-1:0][DataWidth-1:0]
Memory monitor write data
mon_w_id_o: output logic [NumPorts-1:0][IdWidth-1:0]
Memory monitor write ID
mon_w_user_o: output logic [NumPorts-1:0][UserWidth-1:0]
Memory monitor write user
mon_w_beat_count_o: output axi_pkg::len_t [NumPorts-1:0]
Memory monitor write beat count
mon_w_last_o: output logic [NumPorts-1:0]
Memory monitor write last
mon_r_valid_o: output logic [NumPorts-1:0]
Memory monitor read valid. All mon_r_* outputs are only valid if this signal is high.
A read from the memory is visible on the mon_w_* outputs in the clock cycle after it has
happened.
mon_r_addr_o: output logic [NumPorts-1:0][AddrWidth-1:0]
Memory monitor read address
mon_r_data_o: output logic [NumPorts-1:0][DataWidth-1:0]
Memory monitor read data
mon_r_id_o: output logic [NumPorts-1:0][IdWidth-1:0]
Memory monitor read ID
mon_r_user_o: output logic [NumPorts-1:0][UserWidth-1:0]
Memory monitor read user
mon_r_beat_count_o: output axi_pkg::len_t [NumPorts-1:0]
Memory monitor read beat count
mon_r_last_o: output logic [NumPorts-1:0]
Memory monitor read last
Types
| addr_t | |
| data_t | |
| id_t | |
| strb_t | |
| user_t | |
| aw_t | |
| w_t | |
| b_t | |
| ar_t | |
| r_t | |
| monitor_t |