Module axi_sim_mem_multiport_intf
Mutliport interface variant of axi_sim_mem.
See the documentation of the main module for the definition of ports and parameters.
Parameters
AXI_ADDR_WIDTH: int unsigned
AXI_DATA_WIDTH: int unsigned
AXI_ID_WIDTH: int unsigned
AXI_USER_WIDTH: int unsigned
NUM_PORTS: int unsigned
WARN_UNINITIALIZED: bit
UNINITIALIZED_DATA:
ClearErrOnAccess: bit
APPL_DELAY: time
ACQ_DELAY: time
Ports
clk_i: input logic
rst_ni: input logic
axi_slv: AXI_BUS.Slave
mon_w_valid_o: output logic [NUM_PORTS-1:0]
mon_w_addr_o: output logic [NUM_PORTS-1:0][AXI_ADDR_WIDTH-1:0]
mon_w_data_o: output logic [NUM_PORTS-1:0][AXI_DATA_WIDTH-1:0]
mon_w_id_o: output logic [NUM_PORTS-1:0][AXI_ID_WIDTH-1:0]
mon_w_user_o: output logic [NUM_PORTS-1:0][AXI_USER_WIDTH-1:0]
mon_w_beat_count_o: output axi_pkg::len_t [NUM_PORTS-1:0]
mon_w_last_o: output logic [NUM_PORTS-1:0]
mon_r_valid_o: output logic [NUM_PORTS-1:0]
mon_r_addr_o: output logic [NUM_PORTS-1:0][AXI_ADDR_WIDTH-1:0]
mon_r_data_o: output logic [NUM_PORTS-1:0][AXI_DATA_WIDTH-1:0]
mon_r_id_o: output logic [NUM_PORTS-1:0][AXI_ID_WIDTH-1:0]
mon_r_user_o: output logic [NUM_PORTS-1:0][AXI_USER_WIDTH-1:0]
mon_r_beat_count_o: output axi_pkg::len_t [NUM_PORTS-1:0]
mon_r_last_o: output logic [NUM_PORTS-1:0]
Types
| axi_addr_t | |
| axi_data_t | |
| axi_id_t | |
| axi_strb_t | |
| axi_user_t | |
| axi_aw_chan_t | |
| axi_w_chan_t | |
| axi_b_chan_t | |
| axi_ar_chan_t | |
| axi_r_chan_t | |
| axi_req_t | |
| axi_resp_t |