Module axi_slave_compare
Synthesizable test module comparing two AXI slaves of the same type.
The reference response is always passed to the master, whereas the test response
is discarded after handshaking.
This module is meant to be used in FPGA-based verification.
Parameters
AxiIdWidth: int unsigned
ID width of the AXI4+ATOP interface
FifoDepth: int unsigned
FIFO depth
UseSize: bit
Consider size field in comparison
DataWidth: int unsigned
Data width of the AXI4+ATOP interface
axi_aw_chan_t: type
AW channel type of the AXI4+ATOP interface
axi_w_chan_t: type
W channel type of the AXI4+ATOP interface
axi_b_chan_t: type
B channel type of the AXI4+ATOP interface
axi_ar_chan_t: type
AR channel type of the AXI4+ATOP interface
axi_r_chan_t: type
R channel type of the AXI4+ATOP interface
axi_req_t: type
Request struct type of the AXI4+ATOP slave port
axi_rsp_t: type
Response struct type of the AXI4+ATOP slave port
id_t: type
ID type (do not overwrite)
Ports
clk_i: input logic
Clock
rst_ni: input logic
Asynchronous reset, active low
testmode_i: input logic
Testmode
axi_mst_req_i: input axi_req_t
AXI4+ATOP channel request in
axi_mst_rsp_o: output axi_rsp_t
AXI4+ATOP channel response out
axi_ref_req_o: output axi_req_t
AXI4+ATOP reference channel request out
axi_ref_rsp_i: input axi_rsp_t
AXI4+ATOP reference channel response in
axi_test_req_o: output axi_req_t
AXI4+ATOP test channel request out
axi_test_rsp_i: input axi_rsp_t
AXI4+ATOP test channel response in
aw_mismatch_o: output id_t
AW mismatch
w_mismatch_o: output logic
W mismatch
b_mismatch_o: output id_t
B mismatch
ar_mismatch_o: output id_t
AR mismatch
r_mismatch_o: output id_t
R mismatch
mismatch_o: output logic
General mismatch
busy_o: output logic
Unit is busy