Module axi_to_apb
Parameters
NoApbSlaves: int unsigned
Number of connected APB slaves.
NoRules: int unsigned
Number of APB address-decode rules. Set to 0 to omit the address decoder entirely.
NoRules == 0is only legal withNoApbSlaves == 1`.
AxiAddrWidth: int unsigned
AXI4 address width. Decoding uses the full width; paddr is truncated to ApbAddrWidth.
AxiDataWidth: int unsigned
AXI4 data width. Must be an integer power-of-two multiple of ApbDataWidth.
AxiIdWidth: int unsigned
AXI4 ID width.
AxiUserWidth: int unsigned
AXI4 user width.
AxiMaxWriteTxns: int unsigned
Maximum number of outstanding writes tracked by the axi_atop_filter.
BufDepth: int unsigned
Response buffer depth of the internal axi_to_detailed_mem.
OutFifoDepth: int unsigned
Output FIFO depth of the internal axi_to_detailed_mem.
ApbAddrWidth: int unsigned
APB4 address width. Must be <= AxiAddrWidth; the upper AXI address bits are discarded.
ApbDataWidth: int unsigned
APB4 data width. Must be a multiple of 8 and <= 32 (ApbDataWidth == 8 is supported).
axi_req_t: type
AXI4+ATOP request struct, see axi/typedef.svh.
axi_resp_t: type
AXI4+ATOP response struct, see axi/typedef.svh.
apb_req_t: type
APB4 request struct.
apb_resp_t: type
APB4 response struct.
rule_t: type
Address-decode rule struct from common_cells (addr_decode).
UseAddrDecode: bit
NumBanks: int unsigned
SelIdxWidth: int unsigned
BankIdxWidth: int unsigned
Ports
clk_i: input logic
rst_ni: input logic
axi_req_i: input axi_req_t
axi_resp_o: output axi_resp_t
apb_req_o: output apb_req_t [NoApbSlaves-1:0]
apb_resp_i: input apb_resp_t [NoApbSlaves-1:0]
addr_map_i: input rule_t [((NoRules > 0) ? NoRules : 1)-1:0]
Types
| axi_addr_t | |
| apb_addr_t | |
| apb_data_t | |
| apb_strb_t | |
| sel_idx_t | |
| apb_state_e |