Module axi_to_apb_intf
Parameters
NoApbSlaves: int unsigned
Number of connected APB slaves.
NoRules: int unsigned
Number of APB address-decode rules. Set to 0 to omit the address decoder (see axi_to_apb);
only legal with NoApbSlaves == 1, in which case addr_map_i may be left unconnected.
AxiAddrWidth: int unsigned
AXI4 address width. Decoding uses the full width; paddr is truncated to ApbAddrWidth.
AxiDataWidth: int unsigned
AXI4 data width. Must be an integer power-of-two multiple of ApbDataWidth.
AxiIdWidth: int unsigned
AXI4 ID width.
AxiUserWidth: int unsigned
AXI4 user width.
AxiMaxWriteTxns: int unsigned
Maximum number of outstanding writes tracked by the axi_atop_filter.
BufDepth: int unsigned
Response buffer depth of the internal axi_to_detailed_mem.
OutFifoDepth: int unsigned
Output FIFO depth of the internal axi_to_detailed_mem.
ApbAddrWidth: int unsigned
APB4 address width. Must be <= AxiAddrWidth; the upper AXI address bits are discarded.
ApbDataWidth: int unsigned
APB4 data width. Must be a multiple of 8 and <= 32 (ApbDataWidth == 8 is supported).
rule_t: type
Address-decode rule struct from common_cells (addr_decode).
apb_addr_t: type
apb_data_t: type
apb_strb_t: type
sel_t: type
SelIdxWidth: int unsigned
Ports
clk_i: input logic
rst_ni: input logic
slv: AXI_BUS.Slave
paddr_o: output apb_addr_t
pprot_o: output logic [2:0]
pselx_o: output sel_t
penable_o: output logic
pwrite_o: output logic
pwdata_o: output apb_data_t
pstrb_o: output apb_strb_t
pready_i: input logic [NoApbSlaves-1:0]
prdata_i: input apb_data_t [NoApbSlaves-1:0]
pslverr_i: input [NoApbSlaves-1:0]
addr_map_i: input rule_t [((NoRules > 0) ? NoRules : 1)-1:0]
Types
| axi_addr_t | |
| axi_data_t | |
| axi_id_t | |
| axi_strb_t | |
| axi_user_t | |
| apb_req_t | |
| apb_resp_t | |
| aw_chan_t | |
| w_chan_t | |
| b_chan_t | |
| ar_chan_t | |
| r_chan_t | |
| axi_req_t | |
| axi_resp_t |