Module axi_to_axi_lite_intf

Parameters

`AXI_ADDR_WIDTH: int unsigned`

AXI bus parameters

`AXI_DATA_WIDTH: int unsigned`

`AXI_ID_WIDTH: int unsigned`

`AXI_USER_WIDTH: int unsigned`

`AXI_MAX_WRITE_TXNS: int unsigned`

Maximum number of outstanding writes.

`AXI_MAX_READ_TXNS: int unsigned`

Maximum number of outstanding reads.

`FALL_THROUGH: bit`

`FULL_BW: bit`

Ports

`clk_i: input logic`

`rst_ni: input logic`

`testmode_i: input logic`

`slv: AXI_BUS.Slave`

`mst: AXI_LITE.Master`

Types

addr_t
data_t
id_t
strb_t
user_t
full_aw_chan_t
full_w_chan_t
full_b_chan_t
full_ar_chan_t
full_r_chan_t
full_req_t
full_resp_t
lite_aw_chan_t
lite_w_chan_t
lite_b_chan_t
lite_ar_chan_t
lite_r_chan_t
lite_req_t
lite_resp_t

Signals

`full_req: full_req_t`

`full_resp: full_resp_t`

`lite_req: lite_req_t`

`lite_resp: lite_resp_t`