Module axi_to_detailed_mem
AXI4+ATOP slave module which translates AXI bursts into a memory stream.
If both read and write channels of the AXI4+ATOP are active, both will have an
utilization of 50%.
Parameters
axi_req_t: type
AXI4+ATOP request type. See include/axi/typedef.svh.
axi_resp_t: type
AXI4+ATOP response type. See include/axi/typedef.svh.
AddrWidth: int unsigned
Address width, has to be less or equal than the width off the AXI address field.
Determines the width of mem_addr_o. Has to be wide enough to emit the memory region
which should be accessible.
DataWidth: int unsigned
AXI4+ATOP data width.
IdWidth: int unsigned
AXI4+ATOP ID width.
UserWidth: int unsigned
AXI4+ATOP user width.
NumBanks: int unsigned
Number of banks at output, must evenly divide DataWidth.
BufDepth: int unsigned
Depth of memory response buffer. This should be equal to the memory response latency.
HideStrb: bit
Hide write requests if the strb == ’0
OutFifoDepth: int unsigned
Depth of output fifo/fall_through_register. Increase for asymmetric backpressure (contention) on banks.
addr_t: type
Dependent parameter, do not override. Memory address type.
mem_data_t: type
Dependent parameter, do not override. Memory data type.
mem_strb_t: type
Dependent parameter, do not override. Memory write strobe type.
mem_id_t: type
Dependent parameter, do not override. Memory id type.
mem_user_t: type
Dependent parameter, do not override. Memory user type.
NumBytesPerBank:
Ports
clk_i: input logic
Clock input.
rst_ni: input logic
Asynchronous reset, active low.
busy_o: output logic
The unit is busy handling an AXI4+ATOP request.
axi_req_i: input axi_req_t
AXI4+ATOP slave port, request input.
axi_resp_o: output axi_resp_t
AXI4+ATOP slave port, response output.
mem_req_o: output logic [NumBanks-1:0]
Memory stream master, request is valid for this bank.
mem_gnt_i: input logic [NumBanks-1:0]
Memory stream master, request can be granted by this bank.
mem_addr_o: output addr_t [NumBanks-1:0]
Memory stream master, byte address of the request.
mem_wdata_o: output mem_data_t [NumBanks-1:0]
Memory stream master, write data for this bank. Valid when mem_req_o.
mem_strb_o: output mem_strb_t [NumBanks-1:0]
Memory stream master, byte-wise strobe (byte enable).
mem_atop_o: output axi_pkg::atop_t [NumBanks-1:0]
Memory stream master, axi_pkg::atop_t signal associated with this request.
mem_lock_o: output logic [NumBanks-1:0]
Memory stream master, lock signal.
mem_we_o: output logic [NumBanks-1:0]
Memory stream master, write enable. Then asserted store of mem_w_data is requested.
mem_id_o: output mem_id_t [NumBanks-1:0]
Memory stream master, ID. Response ID is managed internally, ensure in-order responses.
mem_user_o: output mem_user_t [NumBanks-1:0]
Memory stream master, user signal. Ax channel user bits used.
mem_cache_o: output axi_pkg::cache_t [NumBanks-1:0]
Memory stream master, cache signal.
mem_prot_o: output axi_pkg::prot_t [NumBanks-1:0]
Memory stream master, protection signal.
mem_qos_o: output axi_pkg::qos_t [NumBanks-1:0]
Memory stream master, QOS signal.
mem_region_o: output axi_pkg::region_t [NumBanks-1:0]
Memory stream master, region signal.
mem_rvalid_i: input logic [NumBanks-1:0]
Memory stream master, response is valid. This module expects always a response valid for a
request regardless if the request was a write or a read.
mem_rdata_i: input mem_data_t [NumBanks-1:0]
Memory stream master, read response data.
mem_err_i: input logic [NumBanks-1:0]
Memory stream master, error response.
mem_exokay_i: input logic [NumBanks-1:0]
Memory stream master, read response exclusive access OK.
Types
| axi_data_t | |
| axi_strb_t | |
| axi_id_t | |
| mem_req_t | |
| meta_t | |
| mem_rsp_t | |
| tmp_atop_t |