Module axi_to_mem_banked
AXI4+ATOP to banked SRAM memory slave. Allows for parallel read and write transactions.
Has higher throughput than axi_to_mem, however needs more hardware.
The used address space starts at 0x0 and ends at the capacity of all memory banks combined.
The higher address bits are ignored for accesses.
Parameters
AxiIdWidth: int unsigned
AXI4+ATOP ID width
AxiAddrWidth: int unsigned
AXI4+ATOP address width
AxiDataWidth: int unsigned
AXI4+ATOP data width
axi_aw_chan_t: type
AXI4+ATOP AW channel struct
axi_w_chan_t: type
AXI4+ATOP W channel struct
axi_b_chan_t: type
AXI4+ATOP B channel struct
axi_ar_chan_t: type
AXI4+ATOP AR channel struct
axi_r_chan_t: type
AXI4+ATOP R channel struct
axi_req_t: type
AXI4+ATOP request struct
axi_resp_t: type
AXI4+ATOP response struct
MemNumBanks: int unsigned
Number of memory banks / macros
Has to satisfy:
-
MemNumBanks >= 2 * AxiDataWidth / MemDataWidth
-
MemNumBanks is a power of 2.
MemAddrWidth: int unsigned
Address width of an individual memory bank. This is treated as a word address.
MemDataWidth: int unsigned
Data width of the memory macros.
Has to satisfy:
- AxiDataWidth % MemDataWidth = 0
MemLatency: int unsigned
Read latency of the connected memory in cycles
HideStrb: bit
Hide write requests if the strb == ’0
OutFifoDepth: int unsigned
Depth of output fifo/fall_through_register. Increase for asymmetric backpressure (contention) on banks.
mem_addr_t: type
DEPENDENT PARAMETER, DO NOT OVERWRITE! Address type of the memory request.
mem_atop_t: type
DEPENDENT PARAMETER, DO NOT OVERWRITE! Atomic operation type for the memory request.
mem_data_t: type
DEPENDENT PARAMETER, DO NOT OVERWRITE! Data type for the memory request.
mem_strb_t: type
DEPENDENT PARAMETER, DO NOT OVERWRITE! Byte strobe/enable signal for the memory request.
BanksPerAxiChannel: int unsigned
This specifies the number of banks needed to have the full data bandwidth of one
AXI data channel.
BankSelOffset: int unsigned
Offset of the byte address from AXI to determine, where the selection signal for the
memory bank should start.
BankSelWidth: int unsigned
Selection signal width of the xbar. This is the reason for power of two banks, otherwise
There are holes in the address mapping.
Ports
clk_i: input logic
Clock
rst_ni: input logic
Asynchronous reset, active low
test_i: input logic
Testmode enable
axi_req_i: input axi_req_t
AXI4+ATOP slave port, request struct
axi_resp_o: output axi_resp_t
AXI4+ATOP slave port, response struct
mem_req_o: output logic [MemNumBanks-1:0]
Memory bank request
mem_gnt_i: input logic [MemNumBanks-1:0]
Memory request grant
mem_add_o: output mem_addr_t [MemNumBanks-1:0]
Request address
mem_we_o: output logic [MemNumBanks-1:0]
Write request enable, active high
mem_wdata_o: output mem_data_t [MemNumBanks-1:0]
Write data
mem_be_o: output mem_strb_t [MemNumBanks-1:0]
Write data byte enable, active high
mem_atop_o: output mem_atop_t [MemNumBanks-1:0]
Atomic operation
mem_rdata_i: input mem_data_t [MemNumBanks-1:0]
Read data response
axi_to_mem_busy_o: output logic [1:0]
Status output, busy flag of axi_to_mem
Types
| xbar_sel_t | |
| access_type_e | |
| axi_addr_t | |
| xbar_payload_t | Payload definition which is sent over the xbar between the macros and the read/write unit. |
| read_sel_t | Read data definition for the shift register, which samples the read response data |