Module axi_to_mem_banked_intf
AXI4+ATOP interface wrapper for axi_to_mem
Parameters
AXI_ID_WIDTH: int unsigned
AXI4+ATOP ID width
AXI_ADDR_WIDTH: int unsigned
AXI4+ATOP address width
AXI_DATA_WIDTH: int unsigned
AXI4+ATOP data width
AXI_USER_WIDTH: int unsigned
AXI4+ATOP user width
MEM_NUM_BANKS: int unsigned
Number of memory banks / macros
Has to satisfy:
-
MemNumBanks >= 2 * AxiDataWidth / MemDataWidth
-
MemNumBanks is a power of 2.
MEM_ADDR_WIDTH: int unsigned
Address width of an individual memory bank.
MEM_DATA_WIDTH: int unsigned
Data width of the memory macros.
Has to satisfy:
- AxiDataWidth % MemDataWidth = 0
MEM_LATENCY: int unsigned
Read latency of the connected memory in cycles
HIDE_STRB: bit
Hide write requests if the strb == ’0
OUT_FIFO_DEPTH: int unsigned
Depth of output fifo/fall_through_register. Increase for asymmetric backpressure (contention) on banks.
mem_addr_t: type
mem_atop_t: type
mem_data_t: type
mem_strb_t: type
Ports
clk_i: input logic
Clock
rst_ni: input logic
Asynchronous reset, active low
test_i: input logic
Testmode enable
slv: AXI_BUS.Slave
AXI4+ATOP slave port
mem_req_o: output logic [MEM_NUM_BANKS-1:0]
Memory bank request
mem_gnt_i: input logic [MEM_NUM_BANKS-1:0]
Memory request grant
mem_add_o: output mem_addr_t [MEM_NUM_BANKS-1:0]
Request address
mem_we_o: output logic [MEM_NUM_BANKS-1:0]
Write request enable, active high
mem_wdata_o: output mem_data_t [MEM_NUM_BANKS-1:0]
Write data
mem_be_o: output mem_strb_t [MEM_NUM_BANKS-1:0]
Write data byte enable, active high
mem_atop_o: output mem_atop_t [MEM_NUM_BANKS-1:0]
Atomic operation
mem_rdata_i: input mem_data_t [MEM_NUM_BANKS-1:0]
Read data response
axi_to_mem_busy_o: output logic [1:0]
Status output, busy flag of axi_to_mem
Types
| id_t | |
| addr_t | |
| data_t | |
| strb_t | |
| user_t | |
| aw_chan_t | |
| w_chan_t | |
| b_chan_t | |
| ar_chan_t | |
| r_chan_t | |
| axi_req_t | |
| axi_resp_t |