Module axi_to_mem_split
AXI4+ATOP to memory-protocol interconnect. Completely separates the read and write channel to
individual mem ports. This can only be used when addresses for the same bank are accessible
from different memory ports.
Parameters
axi_req_t: type
AXI4+ATOP request type. See include/axi/typedef.svh.
axi_resp_t: type
AXI4+ATOP response type. See include/axi/typedef.svh.
AddrWidth: int unsigned
Address width, has to be less or equal than the width off the AXI address field.
Determines the width of mem_addr_o. Has to be wide enough to emit the memory region
which should be accessible.
AxiDataWidth: int unsigned
AXI4+ATOP data width.
IdWidth: int unsigned
AXI4+ATOP ID width.
MemDataWidth: int unsigned
Memory data width, must evenly divide DataWidth.
BufDepth: int unsigned
Depth of memory response buffer. This should be equal to the memory response latency.
HideStrb: bit
Hide write requests if the strb == ’0
OutFifoDepth: int unsigned
Depth of output fifo/fall_through_register. Increase for asymmetric backpressure (contention) on banks.
NumMemPorts: int unsigned
Dependent parameters, do not override. Number of memory ports.
addr_t: type
Dependent parameter, do not override. Memory address type.
mem_data_t: type
Dependent parameter, do not override. Memory data type.
mem_strb_t: type
Dependent parameter, do not override. Memory write strobe type.
Ports
clk_i: input logic
Clock input.
rst_ni: input logic
Asynchronous reset, active low.
test_i: input logic
Testmode enable
busy_o: output logic
The unit is busy handling an AXI4+ATOP request.
axi_req_i: input axi_req_t
AXI4+ATOP slave port, request input.
axi_resp_o: output axi_resp_t
AXI4+ATOP slave port, response output.
mem_req_o: output logic [NumMemPorts-1:0]
Memory stream master, request is valid for this bank.
mem_gnt_i: input logic [NumMemPorts-1:0]
Memory stream master, request can be granted by this bank.
mem_addr_o: output addr_t [NumMemPorts-1:0]
Memory stream master, byte address of the request.
mem_wdata_o: output mem_data_t [NumMemPorts-1:0]
Memory stream master, write data for this bank. Valid when mem_req_o.
mem_strb_o: output mem_strb_t [NumMemPorts-1:0]
Memory stream master, byte-wise strobe (byte enable).
mem_atop_o: output axi_pkg::atop_t [NumMemPorts-1:0]
Memory stream master, axi_pkg::atop_t signal associated with this request.
mem_we_o: output logic [NumMemPorts-1:0]
Memory stream master, write enable. Then asserted store of mem_w_data is requested.
mem_rvalid_i: input logic [NumMemPorts-1:0]
Memory stream master, response is valid. This module expects always a response valid for a
request regardless if the request was a write or a read.
mem_rdata_i: input mem_data_t [NumMemPorts-1:0]
Memory stream master, read response data.