Module axi_to_mem_split_intf
AXI4+ATOP interface wrapper for axi_to_mem_split
Parameters
AXI_ID_WIDTH: int unsigned
AXI4+ATOP ID width
AXI_ADDR_WIDTH: int unsigned
AXI4+ATOP address width
AXI_DATA_WIDTH: int unsigned
AXI4+ATOP data width
AXI_USER_WIDTH: int unsigned
AXI4+ATOP user width
MEM_DATA_WIDTH: int unsigned
Memory data width, must evenly divide DataWidth.
BUF_DEPTH: int unsigned
See axi_to_mem, parameter BufDepth.
HIDE_STRB: bit
Hide write requests if the strb == ’0
OUT_FIFO_DEPTH: int unsigned
Depth of output fifo/fall_through_register. Increase for asymmetric backpressure (contention) on banks.
NUM_MEM_PORTS: int unsigned
Dependent parameters, do not override. Number of memory ports.
addr_t: type
Dependent parameter, do not override. See axi_to_mem, parameter addr_t.
mem_data_t: type
Dependent parameter, do not override. See axi_to_mem, parameter mem_data_t.
mem_strb_t: type
Dependent parameter, do not override. See axi_to_mem, parameter mem_strb_t.
Ports
clk_i: input logic
Clock input.
rst_ni: input logic
Asynchronous reset, active low.
test_i: input logic
Testmode enable
busy_o: output logic
See axi_to_mem_split, port busy_o.
axi_bus: AXI_BUS.Slave
AXI4+ATOP slave interface port.
mem_req_o: output logic [NUM_MEM_PORTS-1:0]
See axi_to_mem_split, port mem_req_o.
mem_gnt_i: input logic [NUM_MEM_PORTS-1:0]
See axi_to_mem_split, port mem_gnt_i.
mem_addr_o: output addr_t [NUM_MEM_PORTS-1:0]
See axi_to_mem_split, port mem_addr_o.
mem_wdata_o: output mem_data_t [NUM_MEM_PORTS-1:0]
See axi_to_mem_split, port mem_wdata_o.
mem_strb_o: output mem_strb_t [NUM_MEM_PORTS-1:0]
See axi_to_mem_split, port mem_strb_o.
mem_atop_o: output axi_pkg::atop_t [NUM_MEM_PORTS-1:0]
See axi_to_mem_split, port mem_atop_o.
mem_we_o: output logic [NUM_MEM_PORTS-1:0]
See axi_to_mem_split, port mem_we_o.
mem_rvalid_i: input logic [NUM_MEM_PORTS-1:0]
See axi_to_mem_split, port mem_rvalid_i.
mem_rdata_i: input mem_data_t [NUM_MEM_PORTS-1:0]
See axi_to_mem_split, port mem_rdata_i.
Types
| id_t | |
| data_t | |
| strb_t | |
| user_t | |
| axi_aw_chan_t | |
| axi_w_chan_t | |
| axi_b_chan_t | |
| axi_ar_chan_t | |
| axi_r_chan_t | |
| axi_req_t | |
| axi_resp_t |