Module axi_xbar
axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports.
See doc/axi_xbar.md for the documentation, including the definition of parameters and ports.
Parameters
Cfg: axi_pkg::xbar_cfg_t
Configuration struct for the crossbar see axi_pkg for fields and definitions.
ATOPs: bit
Enable atomic operations support.
Connectivity: bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0]
Connectivity matrix
slv_aw_chan_t: type
AXI4+ATOP AW channel struct type for the slave ports.
mst_aw_chan_t: type
AXI4+ATOP AW channel struct type for the master ports.
w_chan_t: type
AXI4+ATOP W channel struct type for all ports.
slv_b_chan_t: type
AXI4+ATOP B channel struct type for the slave ports.
mst_b_chan_t: type
AXI4+ATOP B channel struct type for the master ports.
slv_ar_chan_t: type
AXI4+ATOP AR channel struct type for the slave ports.
mst_ar_chan_t: type
AXI4+ATOP AR channel struct type for the master ports.
slv_r_chan_t: type
AXI4+ATOP R channel struct type for the slave ports.
mst_r_chan_t: type
AXI4+ATOP R channel struct type for the master ports.
slv_req_t: type
AXI4+ATOP request struct type for the slave ports.
slv_resp_t: type
AXI4+ATOP response struct type for the slave ports.
mst_req_t: type
AXI4+ATOP request struct type for the master ports.
mst_resp_t: type
AXI4+ATOP response struct type for the master ports
rule_t: type
Address rule type for the address decoders from common_cells:addr_decode.
Example types are provided in axi_pkg.
Required struct fields:
typedef struct packed {
int unsigned idx;
axi_addr_t start_addr;
axi_addr_t end_addr;
} rule_t;
Ports
clk_i: input logic
Clock, positive edge triggered.
rst_ni: input logic
Asynchronous reset, active low.
test_i: input logic
Testmode enable, active high.
slv_ports_req_i: input slv_req_t [Cfg.NoSlvPorts-1:0]
AXI4+ATOP requests to the slave ports.
slv_ports_resp_o: output slv_resp_t [Cfg.NoSlvPorts-1:0]
AXI4+ATOP responses of the slave ports.
mst_ports_req_o: output mst_req_t [Cfg.NoMstPorts-1:0]
AXI4+ATOP requests of the master ports.
mst_ports_resp_i: input mst_resp_t [Cfg.NoMstPorts-1:0]
AXI4+ATOP responses to the master ports.
addr_map_i: input rule_t [Cfg.NoAddrRules-1:0]
Address map array input for the crossbar. This map is global for the whole module.
It is used for routing the transactions to the respective master ports.
Each master port can have multiple different rules.
en_default_mst_port_i: input logic [Cfg.NoSlvPorts-1:0]
Enable default master port.
default_mst_port_i: input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0]
Enables a default master port for each slave port. When this is enabled unmapped
transactions get issued at the master port given by default_mst_port_i.
When not used, tie to '0.