Module axi_zero_mem
AXI4+ATOP slave module which translates AXI bursts into a memory stream
which behaves as a memory containing only 0 data which cannot be
overwritten by write operations.
-
read: grants the request and returns data0. -
write: grants the request, write data goes into nothingness (can be used as data sink)
If both read and write channels of the AXI4+ATOP are active, both will have an
utilization of 50%.
Parameters
axi_req_t: type
AXI4+ATOP request type. See include/axi/typedef.svh.
axi_resp_t: type
AXI4+ATOP response type. See include/axi/typedef.svh.
AddrWidth: int unsigned
Address width, has to be less or equal than the width off the AXI address field.
Determines the width of mem_addr_o. Has to be wide enough to emit the memory region
which should be accessible.
DataWidth: int unsigned
AXI4+ATOP data width.
IdWidth: int unsigned
AXI4+ATOP ID width.
NumBanks: int unsigned
Number of banks at output, must evenly divide DataWidth.
BufDepth: int unsigned
Depth of memory response buffer. This should be equal to the memory response latency.
addr_t: type
Dependent parameter, do not override. Memory address type.
mem_data_t: type
Dependent parameter, do not override. Memory data type.
mem_strb_t: type
Dependent parameter, do not override. Memory write strobe type.
Ports
clk_i: input logic
Clock input.
rst_ni: input logic
Asynchronous reset, active low.
busy_o: output logic
The unit is busy handling an AXI4+ATOP request.
axi_req_i: input axi_req_t
AXI4+ATOP slave port, request input.
axi_resp_o: output axi_resp_t
AXI4+ATOP slave port, response output.