Module mem_stream_to_banks_detailed

Split memory access over multiple parallel banks, where each bank has its own req/gnt

request and valid response direction.

Parameters

AddrWidth: int unsigned

Input address width.

DataWidth: int unsigned

Input data width, must be a power of two.

WUserWidth: int unsigned

Request sideband width.

RUserWidth: int unsigned

Response sideband width.

NumBanks: int unsigned

Number of banks at output, must evenly divide DataWidth.

HideStrb: bit

Remove transactions that have zero strobe

MaxTrans: int unsigned

Number of outstanding transactions

OutFifoDepth: int unsigned

Request FIFO depth

wuser_t: type

Request sideband type.

addr_t: type

Dependent parameter, do not override! Address type.

inp_data_t: type

Dependent parameter, do not override! Input data type.

inp_strb_t: type

Dependent parameter, do not override! Input write strobe type.

inp_ruser_t: type

Dependent parameter, do not override! Input response sideband type.

oup_data_t: type

Dependent parameter, do not override! Output data type.

oup_strb_t: type

Dependent parameter, do not override! Output write strobe type.

oup_ruser_t: type

Dependent parameter, do not override! Output response sideband type.

DataBytes: int unsigned

BitsPerBank: int unsigned

BytesPerBank: int unsigned

Ports

clk_i: input logic

Clock input.

rst_ni: input logic

Asynchronous reset, active low.

req_i: input logic

Memory request to split, request is valid.

gnt_o: output logic

Memory request to split, request can be granted.

addr_i: input addr_t

Memory request to split, request address, byte-wise.

wdata_i: input inp_data_t

Memory request to split, request write data.

strb_i: input inp_strb_t

Memory request to split, request write strobe.

wuser_i: input wuser_t

Memory request to split, request sideband.

we_i: input logic

Memory request to split, request write enable, active high.

rvalid_o: output logic

Memory request to split, response is valid. Required for read and write requests

rready_i: input logic

Memory request to split, response ready input. Tie to 1’b1 if unused.

rdata_o: output inp_data_t

Memory request to split, response read data.

ruser_o: output inp_ruser_t

Memory request to split, response sideband.

bank_req_o: output logic [NumBanks-1:0]

Memory bank request, request is valid.

bank_gnt_i: input logic [NumBanks-1:0]

Memory bank request, request can be granted.

bank_addr_o: output addr_t [NumBanks-1:0]

Memory bank request, request address, byte-wise. Will be different for each bank.

bank_wdata_o: output oup_data_t [NumBanks-1:0]

Memory bank request, request write data.

bank_strb_o: output oup_strb_t [NumBanks-1:0]

Memory bank request, request write strobe.

bank_wuser_o: output wuser_t [NumBanks-1:0]

Memory bank request, request sideband.

bank_we_o: output logic [NumBanks-1:0]

Memory bank request, request write enable, active high.

bank_rvalid_i: input logic [NumBanks-1:0]

Memory bank request, response is valid. Required for read and write requests

bank_rdata_i: input oup_data_t [NumBanks-1:0]

Memory bank request, response read data.

bank_ruser_i: input oup_ruser_t [NumBanks-1:0]

Memory bank request, response sideband.

Types

req_t
cnt_t

Signals

cnt_d: cnt_t

cnt_q: cnt_t