Package axi_pkg

Contains all necessary type definitions, constants, and generally useful functions.

AXI Transaction Burst Width.

AXI Transaction Response Width.

AXI Transaction Cacheability Width.

AXI Transaction Protection Width.

AXI Transaction Quality of Service Width.

AXI Transaction Region Width.

AXI Transaction Length Width.

AXI Transaction Size Width.

AXI Lock Width.

AXI5 Atomic Operation Width.

AXI5 Non-Secure Address Identifier.

In a fixed burst:

• The address is the same for every transfer in the burst.

• The byte lanes that are valid are constant for all beats in the burst. However, within

  those byte lanes, the actual bytes that have wstrb asserted can differ for each beat in

  the burst.

This burst type is used for repeated accesses to the same location such as when loading or

emptying a FIFO.

In an incrementing burst, the address for each transfer in the burst is an increment of the

address for the previous transfer. The increment value depends on the size of the transfer.

For example, the address for each transfer in a burst with a size of 4 bytes is the previous

address plus four.

This burst type is used for accesses to normal sequential memory.

A wrapping burst is similar to an incrementing burst, except that the address wraps around to

a lower address if an upper address limit is reached.

The following restrictions apply to wrapping bursts:

• The start address must be aligned to the size of each transfer.

• The length of the burst must be 2, 4, 8, or 16 transfers.

Normal access success. Indicates that a normal access has been successful. Can also indicate

that an exclusive access has failed.

Exclusive access okay. Indicates that either the read or write portion of an exclusive access

has been successful.

Slave error. Used when the access has reached the slave successfully, but the slave wishes to

return an error condition to the originating master.

Decode error. Generated, typically by an interconnect component, to indicate that there is no

slave at the transaction address.

When this bit is asserted, the interconnect, or any component, can delay the transaction

reaching its final destination for any number of cycles.

When HIGH, Modifiable indicates that the characteristics of the transaction can be modified.

When Modifiable is LOW, the transaction is Non-modifiable.

When this bit is asserted, read allocation of the transaction is recommended but is not

mandatory.

When this bit is asserted, write allocation of the transaction is recommended but is not

mandatory.

• Sends a single data value with an address.

• The target swaps the value at the addressed location with the data value that is supplied in

  the transaction.

• The original data value at the addressed location is returned.

• Outbound data size is 1, 2, 4, or 8 bytes.

• Inbound data size is the same as the outbound data size.

• Sends two data values, the compare value and the swap value, to the addressed location.

  The compare and swap values are of equal size.

• The data value at the addressed location is checked against the compare value:

  • If the values match, the swap value is written to the addressed location.

  • If the values do not match, the swap value is not written to the addressed location.

• The original data value at the addressed location is returned.

• Outbound data size is 2, 4, 8, 16, or 32 bytes.

• Inbound data size is half of the outbound data size because the outbound data contains both

  compare and swap values, whereas the inbound data has only the original data value.

Perform no atomic operation.

• Sends a single data value with an address and the atomic operation to be performed.

• The target performs the operation using the sent data and value at the addressed location as

  operands.

• The result is stored in the address location.

• A single response is given without data.

• Outbound data size is 1, 2, 4, or 8 bytes.

Sends a single data value with an address and the atomic operation to be performed.

• The original data value at the addressed location is returned.

• The target performs the operation using the sent data and value at the addressed location as

  operands.

• The result is stored in the address location.

• Outbound data size is 1, 2, 4, or 8 bytes.

• Inbound data size is the same as the outbound data size.

For AtomicStore and AtomicLoad transactions AWATOP[3] indicates the endianness that is

required for the atomic operation. The value of AWATOP[3] applies to arithmetic operations

only and is ignored for bitwise logical operations.

When deasserted, this bit indicates that the operation is little-endian.

When asserted, this bit indicates that the operation is big-endian.

The value in memory is added to the sent data and the result stored in memory.

Every set bit in the sent data clears the corresponding bit of the data in memory.

Bitwise exclusive OR of the sent data and value in memory.

Every set bit in the sent data sets the corresponding bit of the data in memory.

The value stored in memory is the maximum of the existing value and sent data. This operation

assumes signed data.

The value stored in memory is the minimum of the existing value and sent data. This operation

assumes signed data.

The value stored in memory is the maximum of the existing value and sent data. This operation

assumes unsigned data.

The value stored in memory is the minimum of the existing value and sent data. This operation

assumes unsigned data.

Slice on Demux AW channel.

Slice on Demux W channel.

Slice on Demux B channel.

Slice on Demux AR channel.

Slice on Demux R channel.

Slice on Mux AW channel.

Slice on Mux W channel.

Slice on Mux B channel.

Slice on Mux AR channel.

Slice on Mux R channel.