Package axi_test
A set of testbench utilities for AXI interfaces.
Parameters
AW: int
DW: int
TA: time
TT: time
AW:
IW:
UW:
DW:
UW:
IW:
UW:
DW:
IW:
UW:
AW: int
DW: int
IW: int
UW: int
TA: time
TT: time
AW: int
DW: int
IW: int
UW: int
TA: time
TT: time
MAX_READ_TXNS: int
MAX_WRITE_TXNS: int
AX_MIN_WAIT_CYCLES: int
AX_MAX_WAIT_CYCLES: int
W_MIN_WAIT_CYCLES: int
W_MAX_WAIT_CYCLES: int
RESP_MIN_WAIT_CYCLES: int
RESP_MAX_WAIT_CYCLES: int
SIZE_ALIGN: int
AXI_MAX_BURST_LEN: int
TRAFFIC_SHAPING: int
AXI_EXCLS: bit
AXI_ATOPS: bit
AXI_BURST_FIXED: bit
AXI_BURST_INCR: bit
AXI_BURST_WRAP: bit
UNIQUE_IDS: bit
AXI_STRB_WIDTH: int
N_AXI_IDS: int
AW: int
DW: int
IW: int
UW: int
TA: time
TT: time
RAND_RESP: bit
AX_MIN_WAIT_CYCLES: int
AX_MAX_WAIT_CYCLES: int
R_MIN_WAIT_CYCLES: int
R_MAX_WAIT_CYCLES: int
RESP_MIN_WAIT_CYCLES: int
RESP_MAX_WAIT_CYCLES: int
MAPPED: bit
This parameter eneables an internal memory, which gets randomly initialized, if it is read
and retains written data. This mode does currently not support axi_pkg::BURST_WRAP!
All responses are axi_pkg::RESP_OKAY when in this mode.
AW: int unsigned
DW: int unsigned
TA: time
TT: time
MIN_ADDR: int unsigned
MAX_ADDR: int unsigned
MAX_READ_TXNS: int
MAX_WRITE_TXNS: int
AX_MIN_WAIT_CYCLES: int
AX_MAX_WAIT_CYCLES: int
W_MIN_WAIT_CYCLES: int
W_MAX_WAIT_CYCLES: int
RESP_MIN_WAIT_CYCLES: int
RESP_MAX_WAIT_CYCLES: int
AW: int unsigned
DW: int unsigned
TA: time
TT: time
AX_MIN_WAIT_CYCLES: int
AX_MAX_WAIT_CYCLES: int
R_MIN_WAIT_CYCLES: int
R_MAX_WAIT_CYCLES: int
RESP_MIN_WAIT_CYCLES: int
RESP_MAX_WAIT_CYCLES: int
IW: int unsigned
AXI4+ATOP ID width
AW: int unsigned
AXI4+ATOP address width
DW: int unsigned
AXI4+ATOP data width
UW: int unsigned
AXI4+ATOP user width
TT: time
Stimuli test time
IW: int unsigned
AXI4+ATOP ID width
AW: int unsigned
AXI4+ATOP address width
DW: int unsigned
AXI4+ATOP data width
UW: int unsigned
AXI4+ATOP user width
TT: time
Stimuli test time