Module axi_mux

Parameters

`SlvAxiIDWidth: int unsigned`

`slv_aw_chan_t: type`

`mst_aw_chan_t: type`

`w_chan_t: type`

`slv_b_chan_t: type`

`mst_b_chan_t: type`

`slv_ar_chan_t: type`

`mst_ar_chan_t: type`

`slv_r_chan_t: type`

`mst_r_chan_t: type`

`slv_req_t: type`

`slv_resp_t: type`

`mst_req_t: type`

`mst_resp_t: type`

`NoSlvPorts: int unsigned`

`MaxWTrans: int unsigned`

`FallThrough: bit`

`SpillAw: bit`

`SpillW: bit`

`SpillB: bit`

`SpillAr: bit`

`SpillR: bit`

`MstIdxBits: int unsigned`

`MstAxiIDWidth: int unsigned`

Ports

`clk_i: input logic`

`rst_ni: input logic`

`test_i: input logic`

`slv_reqs_i: input slv_req_t [NoSlvPorts-1:0]`

`slv_resps_o: output slv_resp_t [NoSlvPorts-1:0]`

`mst_req_o: output mst_req_t`

`mst_resp_i: input mst_resp_t`

Types

Signals

`mst_aw_chan: mst_aw_chan_t`

`w_fifo_data: switch_id_t`

`mst_w_chan: w_chan_t`

`switch_b_id: switch_id_t`

`mst_b_chan: mst_b_chan_t`

`mst_ar_chan: mst_ar_chan_t`

`switch_r_id: switch_id_t`

`mst_r_chan: mst_r_chan_t`