Running program: ../sw/bin/test/test_interrupts.hex
-Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace
ClkFrequency:         20MHz
UartRealBaudRate:     113636
@     42100ns | [JTAG] Initialization success
@     42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@     94650ns | [JTAG] Read 0x12345678 from 0x10000000
@     94650ns | [JTAG] Read back correct data
@     94650ns | [JTAG] Loading binary from ../sw/bin/test/test_interrupts.hex
@     96950ns | [JTAG] Writing to memory @10000000 
@    106150ns | [JTAG] Writing to memory @1000000c 
@    119950ns | [JTAG] Writing to memory @10000020 
@   1516050ns | [JTAG] Writing to memory @10000998 
@   1525250ns | [CORE] Waking core via CLINT msip
@   1525250ns | [JTAG] Writing 0x00000001 to 0x02040000
@   1548300ns | [JTAG] Halting hart 0... 
@   1561650ns | [JTAG] Halted
@   1563950ns | [JTAG] Resumed hart 0 
@   1563950ns | [CORE] Wait for end of code...
@   1631850ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 2ms; walltime 1.920 s; speed 849.927 us/s
- Verilator: cpu 1.920 s on 1 threads; alloced 57 MB