=== Simulation flow === ============================================= Phase 1: default config — helloworld ============================================= [INFO][ENV] Croc root: /fosic/designs/croc [INFO][ENV] PDK root: /fosic/designs/croc/technology [INFO][ENV] Croc PDK: sg13cmos5l [INFO][ENV] Active technology view: public mirror [INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout [INFO][ENV] Bender PDK args: -D IHP_SG13CMOS5L=1 [INFO][ENV] Tech LEF: sg13cmos5l_tech.lef [INFO][ENV] IO LEF/GDS: sg13cmos5l_io.lef/sg13cmos5l_io.gds [INFO][ENV] IO Liberty tt/ff: sg13cmos5l_io_typ_1p2V_3p3V_25C.lib/sg13cmos5l_io_fast_1p32V_3p6V_m40C.lib [INFO][ENV] Bondpad LEF/GDS: bondpad5l_70x70.lef/bondpad5l_70x70.gds [INFO][Bender] Generate croc_netlist_yosys.f warning: [W03] Ignoring unknown field `pass_targets` in a dependency in manifest for croc_soc. [INFO][Bender] Remove absolute paths [INFO][Bender] File list generated: croc_netlist_yosys.f [INFO][Verilator] Build Yosys-netlist simulation %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:43:39: Ignoring unsupported: specify block construct 43 | (posedge A1 => (X : A1)) = (0.0,0.0); | ^ ... For warning description see https://verilator.org/warn/SPECIFYIGN?v=5.042 ... Use "/* verilator lint_off SPECIFYIGN */" and lint_on around source to disable this message. %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:104:39: Ignoring unsupported: specify block construct 104 | (posedge A1 => (X : A1)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:165:38: Ignoring unsupported: specify block construct 165 | (posedge A1 => (Y : A1)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:215:38: Ignoring unsupported: specify block construct 215 | (posedge A1 => (Y : A1)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:267:39: Ignoring unsupported: specify block construct 267 | (posedge A1 => (Y : A1)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:386:39: Ignoring unsupported: specify block construct 386 | (posedge A1 => (Y : A1)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:451:36: Ignoring unsupported: specify block construct 451 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:481:36: Ignoring unsupported: specify block construct 481 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:511:36: Ignoring unsupported: specify block construct 511 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:543:36: Ignoring unsupported: specify block construct 543 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:575:36: Ignoring unsupported: specify block construct 575 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:609:36: Ignoring unsupported: specify block construct 609 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:663:36: Ignoring unsupported: specify block construct 663 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:691:36: Ignoring unsupported: specify block construct 691 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:719:36: Ignoring unsupported: specify block construct 719 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:747:36: Ignoring unsupported: specify block construct 747 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:775:36: Ignoring unsupported: specify block construct 775 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:870:44: Ignoring unsupported: specify block construct 870 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:937:44: Ignoring unsupported: specify block construct 937 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1001:44: Ignoring unsupported: specify block construct 1001 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1062:44: Ignoring unsupported: specify block construct 1062 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1117:36: Ignoring unsupported: specify block construct 1117 | (posedge D => (Q : D)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1176:36: Ignoring unsupported: specify block construct 1176 | (posedge D => (Q : D)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1242:36: Ignoring unsupported: specify block construct 1242 | (posedge D => (Q : D)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1308:36: Ignoring unsupported: specify block construct 1308 | (posedge D => (Q : D)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1376:36: Ignoring unsupported: specify block construct 1376 | (posedge D => (Q : D)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1414:36: Ignoring unsupported: specify block construct 1414 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1443:36: Ignoring unsupported: specify block construct 1443 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1472:36: Ignoring unsupported: specify block construct 1472 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1501:36: Ignoring unsupported: specify block construct 1501 | (posedge A => (Z : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1532:36: Ignoring unsupported: specify block construct 1532 | (posedge A => (Z : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1563:36: Ignoring unsupported: specify block construct 1563 | (posedge A => (Z : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1594:36: Ignoring unsupported: specify block construct 1594 | (posedge A => (Z : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1625:36: Ignoring unsupported: specify block construct 1625 | (posedge A => (Z : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1656:36: Ignoring unsupported: specify block construct 1656 | (posedge A => (Z : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1767:36: Ignoring unsupported: specify block construct 1767 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1796:36: Ignoring unsupported: specify block construct 1796 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1825:36: Ignoring unsupported: specify block construct 1825 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1854:36: Ignoring unsupported: specify block construct 1854 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1883:36: Ignoring unsupported: specify block construct 1883 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1934:42: Ignoring unsupported: specify block construct 1934 | (posedge CLK => (GCLK :CLK)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1967:38: Ignoring unsupported: specify block construct 1967 | (posedge A0 => (X : A0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2011:38: Ignoring unsupported: specify block construct 2011 | (posedge A0 => (X : A0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2054:38: Ignoring unsupported: specify block construct 2054 | (posedge A0 => (X : A0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2132:36: Ignoring unsupported: specify block construct 2132 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2166:36: Ignoring unsupported: specify block construct 2166 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2201:40: Ignoring unsupported: specify block construct 2201 | (posedge A_N => (Y : A_N)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2236:40: Ignoring unsupported: specify block construct 2236 | (posedge A_N => (Y : A_N)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2270:36: Ignoring unsupported: specify block construct 2270 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2307:40: Ignoring unsupported: specify block construct 2307 | (posedge A_N => (Y : A_N)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2343:36: Ignoring unsupported: specify block construct 2343 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2381:36: Ignoring unsupported: specify block construct 2381 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2415:36: Ignoring unsupported: specify block construct 2415 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2450:36: Ignoring unsupported: specify block construct 2450 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2485:36: Ignoring unsupported: specify block construct 2485 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2519:36: Ignoring unsupported: specify block construct 2519 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2555:36: Ignoring unsupported: specify block construct 2555 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2591:36: Ignoring unsupported: specify block construct 2591 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2629:36: Ignoring unsupported: specify block construct 2629 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2668:38: Ignoring unsupported: specify block construct 2668 | (posedge A1 => (Y : A1)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2707:36: Ignoring unsupported: specify block construct 2707 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2738:36: Ignoring unsupported: specify block construct 2738 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2769:36: Ignoring unsupported: specify block construct 2769 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2802:36: Ignoring unsupported: specify block construct 2802 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2835:36: Ignoring unsupported: specify block construct 2835 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2870:36: Ignoring unsupported: specify block construct 2870 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2939:44: Ignoring unsupported: specify block construct 2939 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3030:44: Ignoring unsupported: specify block construct 3030 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3115:44: Ignoring unsupported: specify block construct 3115 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3198:44: Ignoring unsupported: specify block construct 3198 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3277:44: Ignoring unsupported: specify block construct 3277 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3350:42: Ignoring unsupported: specify block construct 3350 | (posedge CLK => (GCLK :CLK)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3508:37: Ignoring unsupported: specify block construct 3508 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3559:37: Ignoring unsupported: specify block construct 3559 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct 137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct 137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_256x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct 137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_512x32_c2_bm_bist.v:138:54: Ignoring unsupported: specify block construct 138 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_512x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct 137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct 137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct 137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:89572:70: Instance has missing pin: 'impl_o' 89572 | \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[0].i_sram \gen_sram_bank[0].i_sram ( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:226105:143: ... Location of port declaration 226105 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[0].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o); | ^~~~~~ ... For warning description see https://verilator.org/warn/PINMISSING?v=5.042 ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Warning-PINMISSING: ../yosys/out/netlist_debug.v:89593:70: Instance has missing pin: 'impl_o' 89593 | \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[1].i_sram \gen_sram_bank[1].i_sram ( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:226176:143: ... Location of port declaration 226176 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[1].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o); | ^~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:89710:53: Instance has missing pin: 'tdo_oe_o' 89710 | \dmi_jtag$croc_chip.i_croc_soc.i_croc.i_dmi_jtag i_dmi_jtag ( | ^~~~~~~~~~ ../yosys/out/netlist_debug.v:182560:225: ... Location of port declaration 182560 | module \dmi_jtag$croc_chip.i_croc_soc.i_croc.i_dmi_jtag (clk_i, rst_ni, testmode_i, dmi_rst_no, dmi_req_o, dmi_req_valid_o, dmi_req_ready_i, dmi_resp_i, dmi_resp_ready_o, dmi_resp_valid_i, tck_i, tms_i, trst_ni, td_i, td_o, tdo_oe_o); | ^~~~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:90451:55: Instance has missing pin: 'overflow_o' 90451 | \obi_timer$croc_chip.i_croc_soc.i_croc.i_obi_timer i_obi_timer ( | ^~~~~~~~~~~ ../yosys/out/netlist_debug.v:200104:108: ... Location of port declaration 200104 | module \obi_timer$croc_chip.i_croc_soc.i_croc.i_obi_timer (clk_i, rst_ni, obi_req_i, obi_rsp_o, expired_o, overflow_o); | ^~~~~~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:90486:49: Instance has missing pin: 'irq_no' 90486 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart ( | ^~~~~~ ../yosys/out/netlist_debug.v:204599:142: ... Location of port declaration 204599 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, obi_req_i, obi_rsp_o, irq_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no); | ^~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:90486:49: Instance has missing pin: 'rts_no' 90486 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart ( | ^~~~~~ ../yosys/out/netlist_debug.v:204599:150: ... Location of port declaration 204599 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, obi_req_i, obi_rsp_o, irq_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no); | ^~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:90486:49: Instance has missing pin: 'dtr_no' 90486 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart ( | ^~~~~~ ../yosys/out/netlist_debug.v:204599:158: ... Location of port declaration 204599 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, obi_req_i, obi_rsp_o, irq_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no); | ^~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:90486:49: Instance has missing pin: 'out1_no' 90486 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart ( | ^~~~~~ ../yosys/out/netlist_debug.v:204599:166: ... Location of port declaration 204599 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, obi_req_i, obi_rsp_o, irq_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no); | ^~~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:90486:49: Instance has missing pin: 'out2_no' 90486 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart ( | ^~~~~~ ../yosys/out/netlist_debug.v:204599:175: ... Location of port declaration 204599 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, obi_req_i, obi_rsp_o, irq_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no); | ^~~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:189626:85: Instance has missing pin: 'src_clear_pending_o' 189626 | \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req \i_dmi_cdc.i_cdc_req ( | ^~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:2719:259: ... Location of port declaration 2719 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o); | ^~~~~~~~~~~~~~~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:189644:86: Instance has missing pin: 'dst_clear_pending_o' 189644 | \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp \i_dmi_cdc.i_cdc_resp ( | ^~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:3074:201: ... Location of port declaration 3074 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o); | ^~~~~~~~~~~~~~~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:189644:86: Instance has missing pin: 'src_clear_pending_o' 189644 | \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp \i_dmi_cdc.i_cdc_resp ( | ^~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:3074:260: ... Location of port declaration 3074 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o); | ^~~~~~~~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_verification/clk_rst_gen.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module clk_rst_gen #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.042 ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_sram.sv:56:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 56 | module tc_sram #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_sram_impl.sv:27:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 27 | module tc_sram_impl #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module tc_clk_and2 ( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:21:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 21 | module tc_clk_buffer ( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 31 | module tc_clk_gating #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:56:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 56 | module tc_clk_inverter ( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:75:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 75 | module tc_clk_mux2 ( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:86:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 86 | module tc_clk_xor2 ( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:96:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 96 | module tc_clk_or2 ( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 107 | module tc_clk_delay #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/binary_to_gray.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module binary_to_gray #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cb_filter_pkg.sv:14:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 14 | package cb_filter_pkg; | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cc_onehot.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module cc_onehot #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_reset_ctrlr_pkg.sv:18:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | package cdc_reset_ctrlr_pkg; | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cf_math_pkg.sv:18:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | package cf_math_pkg; | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/clk_int_div.sv:70:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 70 | module clk_int_div #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/credit_counter.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module credit_counter #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/delta_counter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module delta_counter #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/ecc_pkg.sv:15:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | package ecc_pkg; | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/edge_propagator_tx.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module edge_propagator_tx ( | ^~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/exp_backoff.sv:25:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 25 | module exp_backoff #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/fifo_v3.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module fifo_v3 #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/gray_to_binary.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module gray_to_binary #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/heaviside.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module heaviside #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/isochronous_4phase_handshake.sv:44:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 44 | module isochronous_4phase_handshake ( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/isochronous_spill_register.sv:41:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 41 | module isochronous_spill_register #( | ^~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/lfsr.sv:24:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 24 | module lfsr #( | ^~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/lfsr_16bit.sv:23:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 23 | module lfsr_16bit #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/lfsr_8bit.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module lfsr_8bit #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/lossy_valid_to_stream.sv:49:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 49 | module lossy_valid_to_stream #( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/mv_filter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module mv_filter #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/onehot_to_bin.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module onehot_to_bin #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/plru_tree.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module plru_tree #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/passthrough_stream_fifo.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module passthrough_stream_fifo #( | ^~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/popcount.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 22 | module popcount #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/ring_buffer.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 22 | module ring_buffer #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/rr_arb_tree.sv:49:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 49 | module rr_arb_tree #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/rstgen_bypass.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module rstgen_bypass #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/serial_deglitch.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module serial_deglitch #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/shift_reg.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module shift_reg #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/shift_reg_gated.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module shift_reg_gated #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/spill_register_flushable.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module spill_register_flushable #( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_demux.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module stream_demux #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_filter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module stream_filter ( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fork.sv:21:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 21 | module stream_fork #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_join_dynamic.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 20 | module stream_join_dynamic #( | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_mux.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module stream_mux #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_throttle.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module stream_throttle #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/sub_per_hash.sv:39:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 39 | module sub_per_hash #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/sync.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module sync #( | ^~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/sync_wedge.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module sync_wedge #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/unread.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module unread ( | ^~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/read.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module read #( | ^~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/addr_decode_dync.sv:40:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 40 | module addr_decode_dync #( | ^~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/boxcar.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module boxcar #( | ^~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase.sv:43:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 43 | module cdc_2phase #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase.sv:92:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 92 | module cdc_2phase_src #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase.sv:142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 142 | module cdc_2phase_dst #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_4phase.sv:36:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 36 | module cdc_4phase #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_4phase.sv:92:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 92 | module cdc_4phase_src #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_4phase.sv:205:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 205 | module cdc_4phase_dst #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/clk_int_div_static.sv:60:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 60 | module clk_int_div_static #( | ^~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/trip_counter.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module trip_counter #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/addr_decode.sv:35:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 35 | module addr_decode #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/addr_decode_napot.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module addr_decode_napot #( | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/multiaddr_decode.sv:32:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 32 | module multiaddr_decode #( | ^~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cb_filter.sv:45:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 45 | module cb_filter #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cb_filter.sv:203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 203 | module hash_block #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_2phase.sv:47:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 47 | module cdc_fifo_2phase #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/clk_mux_glitch_free.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 73 | module clk_mux_glitch_free #( | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/clk_mux_glitch_free.sv:256:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 256 | module clk_or_tree #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/counter.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 14 | module counter #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/ecc_decode.sv:29:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 29 | module ecc_decode import ecc_pkg::*; #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/ecc_encode.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 22 | module ecc_encode import ecc_pkg::*; #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/edge_detect.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 14 | module edge_detect ( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/lzc.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module lzc #( | ^~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/max_counter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module max_counter #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/rstgen.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module rstgen ( | ^~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/spill_register.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module spill_register #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_delay.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 14 | module stream_delay #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fifo.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module stream_fifo #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fork_dynamic.sv:24:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 24 | module stream_fork_dynamic #( | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_join.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module stream_join #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_reset_ctrlr.sv:109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 109 | module cdc_reset_ctrlr | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_reset_ctrlr.sv:187:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 187 | module cdc_reset_ctrlr_half | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 103 | module cdc_fifo_gray #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray.sv:171:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 171 | module cdc_fifo_gray_src #( | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray.sv:231:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 231 | module cdc_fifo_gray_dst #( | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/fall_through_register.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module fall_through_register #( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/id_queue.sv:50:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 50 | module id_queue #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_to_mem.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module stream_to_mem #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_arbiter_flushable.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module stream_arbiter_flushable #( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fifo_optimal_wrap.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module stream_fifo_optimal_wrap #( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_register.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module stream_register #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_xbar.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module stream_xbar #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray_clearable.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 103 | module cdc_fifo_gray_clearable #( | ^~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray_clearable.sv:268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 268 | module cdc_fifo_gray_src_clearable #( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray_clearable.sv:328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 328 | module cdc_fifo_gray_dst_clearable #( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase_clearable.sv:54:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 54 | module cdc_2phase_clearable #( | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase_clearable.sv:199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 199 | module cdc_2phase_src_clearable #( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase_clearable.sv:269:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 269 | module cdc_2phase_dst_clearable #( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/mem_to_banks_detailed.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module mem_to_banks_detailed #( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_arbiter.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module stream_arbiter #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_omega_net.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 20 | module stream_omega_net #( | ^~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/mem_to_banks.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module mem_to_banks #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_pkg.sv:7:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | package obi_pkg; | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_rready_converter.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | module obi_rready_converter #( | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/apb_to_obi.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module apb_to_obi #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_to_apb.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module obi_to_apb #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_atop_resolver.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module obi_atop_resolver | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_atop_resolver.sv:536:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 536 | module obi_atop_resolver_intf | ^~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_cut.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | module obi_cut #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_demux.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | module obi_demux #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_demux.sv:114:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 114 | module obi_demux_intf #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_err_sbr.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | module obi_err_sbr #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_err_sbr.sv:69:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 69 | module obi_err_sbr_intf #( | ^~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_mux.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module obi_mux #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_mux.sv:166:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 166 | module obi_mux_intf #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_sram_shim.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | module obi_sram_shim #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_xbar.sv:8:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8 | module obi_xbar #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_xbar.sv:161:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 161 | module obi_xbar_intf #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/apb/apb_pkg.sv:15:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | package apb_pkg; | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_pkg.sv:10:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | package cve2_pkg; | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_alu.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module cve2_alu #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_branch_predict.sv:21:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 21 | module cve2_branch_predict ( | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_compressed_decoder.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module cve2_compressed_decoder ( | ^~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_controller.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module cve2_controller #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_counter.sv:6:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 6 | module cve2_counter #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_csr.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module cve2_csr #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_decoder.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module cve2_decoder #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_fetch_fifo.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module cve2_fetch_fifo #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_load_store_unit.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module cve2_load_store_unit | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_multdiv_fast.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module cve2_multdiv_fast #( | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_multdiv_slow.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module cve2_multdiv_slow | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_pmp.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9 | module cve2_pmp #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_register_file_ff.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 14 | module cve2_register_file_ff #( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_wb.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module cve2_wb #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_cs_registers.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module cve2_cs_registers #( | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_ex_block.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module cve2_ex_block #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_id_stage.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 20 | module cve2_id_stage #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_prefetch_buffer.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module cve2_prefetch_buffer #( | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_if_stage.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module cve2_if_stage import cve2_pkg::*; ( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_core.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module cve2_core import cve2_pkg::*; #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_pkg.sv:11:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | package idma_pkg; | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_channel_coupler.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module idma_channel_coupler #( | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_dataflow_element.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module idma_dataflow_element #( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_obi_read.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module idma_obi_read #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_obi_write.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module idma_obi_write #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_nd_midend.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module idma_nd_midend #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_nd_midend.sv:252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 252 | module idma_nd_counter #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_transfer_id_gen.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9 | module idma_transfer_id_gen #( | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_legalizer_page_splitter.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9 | module idma_legalizer_page_splitter #( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_transport_layer_rw_obi.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module idma_transport_layer_rw_obi #( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_legalizer_rw_obi.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module idma_legalizer_rw_obi #( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_backend_rw_obi.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module idma_backend_rw_obi #( | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/croc_idma.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module croc_idma #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_pkg.sv:9:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9 | package obi_uart_pkg; | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_baudgen.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module obi_uart_baudgen import obi_uart_pkg::*; #() | ^~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_interrupts.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module obi_uart_interrupts import obi_uart_pkg::*; #() | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_modem.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module obi_uart_modem import obi_uart_pkg::*; #() | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_rx.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module obi_uart_rx import obi_uart_pkg::*; #() | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_tx.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module obi_uart_tx #() | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_register.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module obi_uart_register import obi_uart_pkg::*; #( | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module obi_uart #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_pkg.sv:19:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | package dm; | ^~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/debug_rom/debug_rom.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module debug_rom ( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module debug_rom_one_scratch ( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_csrs.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module dm_csrs #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_mem.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module dm_mem #( | ^~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dmi_cdc.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module dmi_cdc ( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dmi_jtag_tap.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module dmi_jtag_tap #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_sba.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module dm_sba #( | ^~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_top.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 20 | module dm_top #( | ^~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dmi_jtag.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module dmi_jtag #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_obi_top.sv:63:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 63 | module dm_obi_top #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/tb/jtag_test_simple.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module jtag_driver_simple #( | ^~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/tb/jtag_test_simple.sv:163:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 163 | module riscv_dbg_simple #( | ^~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/croc_pkg.sv:12:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | package croc_pkg; | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/user_pkg.sv:10:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | package user_pkg; | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/soc_ctrl/soc_ctrl_regs_pkg.sv:8:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8 | package soc_ctrl_regs_pkg; | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/gpio/gpio_reg_pkg.sv:10:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | package gpio_reg_pkg; | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/clint/clint_reg_pkg.sv:8:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8 | package clint_reg_pkg; | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_timer/obi_timer_reg_pkg.sv:8:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8 | package obi_timer_reg_pkg; | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:4:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 4 | module \bootrom$croc_chip.i_croc_soc.i_croc.i_bootrom (clk_i, rst_ni, obi_req_i, obi_rsp_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:2719:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 2719 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:3074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 3074 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:3401:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 3401 | module \cdc_2phase_dst_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_dst (clk_i, rst_ni, data_o, clear_i, ready_i, valid_o, async_req_i, async_ack_o, async_data_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:4730:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 4730 | module \cdc_2phase_dst_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_dst (clk_i, rst_ni, data_o, clear_i, ready_i, valid_o, async_req_i, async_ack_o, async_data_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:5858:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 5858 | module \cdc_2phase_src_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_src (clk_i, rst_ni, data_i, clear_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:7164:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7164 | module \cdc_2phase_src_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_src (clk_i, rst_ni, data_i, clear_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:8269:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8269 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, ready_i, valid_o, async_req_i, async_ack_o, async_data_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:8412:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8412 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, ready_i, valid_o, async_req_i, async_ack_o, async_data_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:8555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8555 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, ready_i, valid_o, async_req_i, async_ack_o, async_data_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:8698:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8698 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, ready_i, valid_o, async_req_i, async_ack_o, async_data_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:8841:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8841 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9060 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9279:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9279 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9498:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9498 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9717 | module \cdc_reset_ctrlr$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr (a_clk_i, a_rst_ni, a_clear_i, a_clear_o, a_clear_ack_i, a_isolate_o, a_isolate_ack_i, b_clk_i, b_rst_ni, b_clear_i, b_clear_o, b_clear_ack_i, b_isolate_o, b_isolate_ack_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9847:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9847 | module \cdc_reset_ctrlr$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr (a_clk_i, a_rst_ni, a_clear_i, a_clear_o, a_clear_ack_i, a_isolate_o, a_isolate_ack_i, b_clk_i, b_rst_ni, b_clear_i, b_clear_o, b_clear_ack_i, b_isolate_o, b_isolate_ack_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9977:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9977 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:10597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10597 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11217:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11217 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11842:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11842 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:12462:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12462 | module \clint$croc_chip.i_croc_soc.i_croc.i_clint (clk_i, rst_ni, obi_req_i, obi_rsp_o, rtc_i, software_irq_o, timer_irq_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:18821:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18821 | module \core_wrap$croc_chip.i_croc_soc.i_croc.i_core_wrap (clk_i, rst_ni, core_busy_o, test_enable_i, irqs_i, timer_irq_i, software_irq_i, boot_addr_i, instr_req_o, instr_gnt_i, instr_rvalid_i, instr_addr_o, instr_rdata_i, instr_err_i, data_req_o, data_gnt_i, data_rvalid_i, data_we_o, data_be_o, data_addr_o, data_wdata_o | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:56643:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 56643 | module croc_chip(clk_i, rst_ni, ref_clk_i, jtag_tck_i, jtag_trst_ni, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, uart_rx_i, uart_tx_o, testmode_i, status_o, gpio0_io, gpio1_io, gpio2_io, gpio3_io, gpio4_io, gpio5_io, gpio6_io, gpio7_io, gpio8_io | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:57633:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 57633 | module \croc_domain$croc_chip.i_croc_soc.i_croc (clk_i, rst_ni, ref_clk_i, jtag_tck_i, jtag_trst_ni, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, uart_rx_i, uart_tx_o, testmode_i, gpio_i, gpio_o, gpio_out_en_o, gpio_in_sync_o, user_sbr_obi_req_o, user_sbr_obi_rsp_i, user_mgr_obi_req_i, user_mgr_obi_rsp_o, interrupts_i, core_busy_o | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:90518:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 90518 | module \croc_soc$croc_chip.i_croc_soc (clk_i, rst_ni, ref_clk_i, jtag_tck_i, jtag_trst_ni, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, uart_rx_i, uart_tx_o, testmode_i, status_o, gpio_i, gpio_o, gpio_out_en_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:91474:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 91474 | module \cve2_cs_registers$croc_chip.i_croc_soc.i_croc.i_core_wrap.i_core.cs_registers_i (clk_i, rst_ni, boot_addr_i, hart_id_i, irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_pending_o, pc_id_i, priv_mode_id_o, priv_mode_lsu_o, csr_mstatus_tw_o, csr_mtvec_o, csr_mtvec_init_i, csr_access_i, csr_addr_i, csr_wdata_i, csr_op_i, csr_op_en_i, csr_rdata_o | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:115833:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 115833 | module \cve2_register_file_ff$croc_chip.i_croc_soc.i_croc.i_core_wrap.i_core.register_file_i (clk_i, rst_ni, test_en_i, raddr_a_i, rdata_a_o, raddr_b_i, rdata_b_o, waddr_a_i, wdata_a_i, we_a_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:146702:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 146702 | module \dm_top$croc_chip.i_croc_soc.i_croc.i_dm_top.i_dm_top (clk_i, rst_ni, testmode_i, debug_req_o, unavailable_i, hartinfo_i, slave_req_i, slave_we_i, slave_addr_i, slave_be_i, slave_wdata_i, slave_rdata_o, master_req_o, master_we_o, master_wdata_o, master_be_o, master_gnt_i, dmi_rst_ni, dmi_req_valid_i, dmi_req_ready_o, dmi_req_i | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:182560:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 182560 | module \dmi_jtag$croc_chip.i_croc_soc.i_croc.i_dmi_jtag (clk_i, rst_ni, testmode_i, dmi_rst_no, dmi_req_o, dmi_req_valid_o, dmi_req_ready_i, dmi_resp_i, dmi_resp_ready_o, dmi_resp_valid_i, tck_i, tms_i, trst_ni, td_i, td_o, tdo_oe_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:190055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 190055 | module \gpio$croc_chip.i_croc_soc.i_croc.i_gpio (clk_i, rst_ni, gpio_i, gpio_o, gpio_out_en_o, gpio_in_sync_o, obi_req_i, obi_rsp_o, interrupt_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 200104 | module \obi_timer$croc_chip.i_croc_soc.i_croc.i_obi_timer (clk_i, rst_ni, obi_req_i, obi_rsp_o, expired_o, overflow_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:204599:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 204599 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, obi_req_i, obi_rsp_o, irq_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:220883:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 220883 | module \soc_ctrl_regs$croc_chip.i_croc_soc.i_croc.i_soc_ctrl (clk_i, rst_ni, obi_req_i, obi_rsp_o, fetch_en_o, sram_dly_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:223776:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 223776 | module \sync$croc_chip.i_croc_soc.i_croc.i_clint.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:223819:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 223819 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:223862:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 223862 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:223905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 223905 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:223948:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 223948 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:223991:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 223991 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_dst.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224045 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_src.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224099 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224142 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224185:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224185 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224228:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224228 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224271 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_dst.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224325:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224325 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_src.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224379:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224379 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[0].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224422:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224422 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[10].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224465 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[11].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224508:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224508 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[12].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224551 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[13].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224594:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224594 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[14].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224637 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[15].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224680:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224680 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[16].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224723:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224723 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[17].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224766 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[18].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224809 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[19].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224852 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[1].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224895:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224895 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[20].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224938:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224938 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[21].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 224981 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[22].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225024:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225024 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[23].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225067 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[24].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225110:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225110 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[25].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225153:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225153 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[26].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225196:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225196 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[27].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225239:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225239 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[28].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225282:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225282 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[29].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225325:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225325 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[2].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225368:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225368 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[30].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225411 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[31].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225454:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225454 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[3].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225497 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[4].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225540 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[5].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225583:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225583 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[6].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225626:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225626 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[7].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225669 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[8].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225712:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225712 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[9].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225755:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225755 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_cd (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225798:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225798 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_cts (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225841:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225841 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_dsr (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225884:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225884 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_ri (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225927:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225927 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_rx.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225970:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225970 | module \tc_clk_inverter$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_jtag_tap.i_tck_inv (clk_i, clk_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:225989:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 225989 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_jtag_tap.i_dft_tck_mux (clk0_i, clk1_i, clk_sel_i, clk_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:226018:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 226018 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_rstgen.i_rstgen_bypass.i_tc_clk_mux2_init_no (clk0_i, clk1_i, clk_sel_i, clk_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:226047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 226047 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_rstgen.i_rstgen_bypass.i_tc_clk_mux2_rst_n (clk0_i, clk1_i, clk_sel_i, clk_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:226076:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 226076 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_rstgen.i_rstgen_bypass.i_tc_clk_mux2_rst_no (clk0_i, clk1_i, clk_sel_i, clk_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:226105:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 226105 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[0].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:226176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 226176 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[1].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:226247:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 226247 | module \user_domain$croc_chip.i_croc_soc.i_user (clk_i, rst_ni, ref_clk_i, testmode_i, user_sbr_obi_req_i, user_sbr_obi_rsp_o, user_mgr_obi_req_o, user_mgr_obi_rsp_i, gpio_in_sync_i, interrupts_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/test/tb_croc_pkg.sv:9:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9 | package tb_croc_pkg; | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/test/croc_vip.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9 | module croc_vip #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/test/tb_croc_soc.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module tb_croc_soc #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:226316:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_user.$abc$177460$new_n118' 226316 | wire \$abc$177460$new_n118 ; | ^~~~~~~~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=5.042 ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. ../yosys/out/netlist_debug.v:226316:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$177460$new_n118 ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:226327:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$177460$new_n129 ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:226328:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$177460$new_n130 ../yosys/out/netlist_debug.v:226940:64: Example path: ASSIGNW ../yosys/out/netlist_debug.v:226270:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o ../yosys/out/netlist_debug.v:18865:9: Example path: ASSIGNW ../yosys/out/netlist_debug.v:18865:9: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.instr_rvalid_i ../technology/verilog/sg13g2_stdcell.v:2265:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58077:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n1880 ../technology/verilog/sg13g2_stdcell.v:570:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58160:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n1964 ../technology/verilog/sg13g2_stdcell.v:1762:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:57824:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$flatten___VhshlaTPZq7HEBjKpnLf9suYGKjfLQAvBAXOP6EhWyVd ../technology/verilog/sg13g2_stdcell.v:37:5: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58495:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2311 ../technology/verilog/sg13g2_stdcell.v:2514:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58498:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2314 ../technology/verilog/sg13g2_stdcell.v:2663:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58507:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2323 ../technology/verilog/sg13g2_stdcell.v:2376:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62109:8: Example path: tb_croc_soc.i_croc_soc.i_croc.all_periph_obi_req_407_ ../yosys/out/netlist_debug.v:61998:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:204610:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__i_uart__obi_req_i ../yosys/out/netlist_debug.v:220879:47: Example path: ASSIGNW ../yosys/out/netlist_debug.v:204614:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o ../technology/verilog/sg13g2_stdcell.v:261:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:57905:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n1706 ../technology/verilog/sg13g2_stdcell.v:2663:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58411:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2216 ../technology/verilog/sg13g2_stdcell.v:446:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58412:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2217 ../technology/verilog/sg13g2_stdcell.v:2663:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58413:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2218 ../technology/verilog/sg13g2_stdcell.v:2702:5: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58998:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2999 ../technology/verilog/sg13g2_stdcell.v:2376:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61998:8: Example path: tb_croc_soc.i_croc_soc.i_croc.all_periph_obi_req_370_ ../yosys/out/netlist_debug.v:61998:8: Example path: ASSIGNW %Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:226349:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_user.$abc$177460$new_n156' 226349 | wire \$abc$177460$new_n156 ; | ^~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:226349:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$177460$new_n156 ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:226327:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$177460$new_n129 ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:226328:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$177460$new_n130 ../yosys/out/netlist_debug.v:226940:64: Example path: ASSIGNW ../yosys/out/netlist_debug.v:226270:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o ../yosys/out/netlist_debug.v:18865:9: Example path: ASSIGNW ../yosys/out/netlist_debug.v:18865:9: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.instr_rvalid_i ../technology/verilog/sg13g2_stdcell.v:2265:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58077:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n1880 ../technology/verilog/sg13g2_stdcell.v:570:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58160:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n1964 ../technology/verilog/sg13g2_stdcell.v:1762:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:57824:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$flatten___VhshlaTPZq7HEBjKpnLf9suYGKjfLQAvBAXOP6EhWyVd ../technology/verilog/sg13g2_stdcell.v:37:5: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58495:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2311 ../technology/verilog/sg13g2_stdcell.v:2514:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58498:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2314 ../technology/verilog/sg13g2_stdcell.v:2663:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58507:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2323 ../technology/verilog/sg13g2_stdcell.v:2376:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62109:8: Example path: tb_croc_soc.i_croc_soc.i_croc.all_periph_obi_req_407_ ../yosys/out/netlist_debug.v:61998:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:204610:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__i_uart__obi_req_i ../yosys/out/netlist_debug.v:220879:47: Example path: ASSIGNW ../yosys/out/netlist_debug.v:204614:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o ../technology/verilog/sg13g2_stdcell.v:261:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:57905:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n1706 ../technology/verilog/sg13g2_stdcell.v:2663:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58411:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2216 ../technology/verilog/sg13g2_stdcell.v:446:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58412:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2217 ../technology/verilog/sg13g2_stdcell.v:2663:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58413:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2218 ../technology/verilog/sg13g2_stdcell.v:2702:5: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58998:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2999 ../technology/verilog/sg13g2_stdcell.v:2376:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61998:8: Example path: tb_croc_soc.i_croc_soc.i_croc.all_periph_obi_req_370_ ../yosys/out/netlist_debug.v:61998:8: Example path: ASSIGNW %Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:226315:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_user.$abc$177460$new_n117' 226315 | wire \$abc$177460$new_n117 ; | ^~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:226315:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$177460$new_n117 ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:226327:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$177460$new_n129 ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:226328:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$177460$new_n130 ../yosys/out/netlist_debug.v:226940:64: Example path: ASSIGNW ../yosys/out/netlist_debug.v:226270:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o ../yosys/out/netlist_debug.v:18865:9: Example path: ASSIGNW ../yosys/out/netlist_debug.v:18865:9: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.instr_rvalid_i ../technology/verilog/sg13g2_stdcell.v:2265:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58077:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n1880 ../technology/verilog/sg13g2_stdcell.v:570:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58160:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n1964 ../technology/verilog/sg13g2_stdcell.v:1762:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:57824:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$flatten___VhshlaTPZq7HEBjKpnLf9suYGKjfLQAvBAXOP6EhWyVd ../technology/verilog/sg13g2_stdcell.v:37:5: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58495:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2311 ../technology/verilog/sg13g2_stdcell.v:2514:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58498:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2314 ../technology/verilog/sg13g2_stdcell.v:2663:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58507:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2323 ../technology/verilog/sg13g2_stdcell.v:2376:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62109:8: Example path: tb_croc_soc.i_croc_soc.i_croc.all_periph_obi_req_407_ ../yosys/out/netlist_debug.v:61998:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:204610:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__i_uart__obi_req_i ../yosys/out/netlist_debug.v:220879:47: Example path: ASSIGNW ../yosys/out/netlist_debug.v:204614:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o ../technology/verilog/sg13g2_stdcell.v:261:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:57905:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n1706 ../technology/verilog/sg13g2_stdcell.v:2663:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58411:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2216 ../technology/verilog/sg13g2_stdcell.v:446:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58412:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2217 ../technology/verilog/sg13g2_stdcell.v:2663:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58413:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2218 ../technology/verilog/sg13g2_stdcell.v:2702:5: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58998:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2999 ../technology/verilog/sg13g2_stdcell.v:2376:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61998:8: Example path: tb_croc_soc.i_croc_soc.i_croc.all_periph_obi_req_370_ ../yosys/out/netlist_debug.v:61998:8: Example path: ASSIGNW %Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:57905:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n1706' 57905 | wire \$abc$158135$new_n1706 ; | ^~~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:57905:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n1706 ../technology/verilog/sg13g2_stdcell.v:2663:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58411:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2216 ../technology/verilog/sg13g2_stdcell.v:446:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58412:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2217 ../technology/verilog/sg13g2_stdcell.v:2663:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58413:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2218 ../technology/verilog/sg13g2_stdcell.v:2702:5: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58998:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n2999 ../technology/verilog/sg13g2_stdcell.v:2376:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61998:8: Example path: tb_croc_soc.i_croc_soc.i_croc.all_periph_obi_req_370_ ../yosys/out/netlist_debug.v:61998:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:204610:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__i_uart__obi_req_i ../yosys/out/netlist_debug.v:220879:47: Example path: ASSIGNW ../yosys/out/netlist_debug.v:204614:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o ../technology/verilog/sg13g2_stdcell.v:261:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:57905:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$158135$new_n1706 make: Entering directory '/fosic/designs/croc/verilator/obj_dir_netlist_yosys' ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /foss/tools/verilator/share/verilator/include/verilated.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_dpi.o /foss/tools/verilator/share/verilator/include/verilated_dpi.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /foss/tools/verilator/share/verilator/include/verilated_timing.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /foss/tools/verilator/share/verilator/include/verilated_threads.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_croc_soc__pch.h -o Vtb_croc_soc__pch.h.fast.gch ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_croc_soc__pch.h -o Vtb_croc_soc__pch.h.slow.gch echo "" > Vtb_croc_soc__ALL.verilator_deplist.tmp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc_vm_classes_0.o Vtb_croc_soc_vm_classes_0.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc_vm_classes_1.o Vtb_croc_soc_vm_classes_1.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc_vm_classes_2.o Vtb_croc_soc_vm_classes_2.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc_vm_classes_3.o Vtb_croc_soc_vm_classes_3.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__Dpi.o Vtb_croc_soc__Dpi.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__ConstPool_0.o Vtb_croc_soc__ConstPool_0.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__Slow.o Vtb_croc_soc___024root__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__0__Slow.o Vtb_croc_soc___024root__0__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__1__Slow.o Vtb_croc_soc___024root__1__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__2__Slow.o Vtb_croc_soc___024root__2__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__3__Slow.o Vtb_croc_soc___024root__3__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__4__Slow.o Vtb_croc_soc___024root__4__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__Syms.o Vtb_croc_soc__Syms.cpp g++ -fuse-ld=mold verilated.o verilated_dpi.o verilated_timing.o verilated_threads.o Vtb_croc_soc__ALL.a -pthread -lpthread -latomic -o Vtb_croc_soc rm Vtb_croc_soc__ALL.verilator_deplist.tmp make: Leaving directory '/fosic/designs/croc/verilator/obj_dir_netlist_yosys' - V e r i l a t i o n R e p o r t: Verilator 5.042 2025-11-02 rev v5.042 - Verilator: Built from 210.399 MB sources in 401 modules, into 34.683 MB in 30 C++ files needing 0.027 MB - Verilator: Walltime 289.061 s (elab=0.780, cvt=9.823, bld=276.959); cpu 12.579 s on 4 threads; alloced 798.844 MB [INFO][ENV] Croc root: /fosic/designs/croc [INFO][ENV] PDK root: /fosic/designs/croc/technology [INFO][ENV] Croc PDK: sg13cmos5l [INFO][ENV] Active technology view: public mirror [INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout [INFO][ENV] Bender PDK args: -D IHP_SG13CMOS5L=1 [INFO][ENV] Tech LEF: sg13cmos5l_tech.lef [INFO][ENV] IO LEF/GDS: sg13cmos5l_io.lef/sg13cmos5l_io.gds [INFO][ENV] IO Liberty tt/ff: sg13cmos5l_io_typ_1p2V_3p3V_25C.lib/sg13cmos5l_io_fast_1p32V_3p6V_m40C.lib [INFO][ENV] Bondpad LEF/GDS: bondpad5l_70x70.lef/bondpad5l_70x70.gds [INFO][Verilator] Run Yosys-netlist simulation Running program: ../sw/bin/helloworld.hex -Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace ClkFrequency: 20MHz UartRealBaudRate: 113636 @ 42100ns | [JTAG] Initialization success @ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000 @ 94650ns | [JTAG] Read 0x12345678 from 0x10000000 @ 94650ns | [JTAG] Read back correct data @ 94650ns | [JTAG] Loading binary from ../sw/bin/helloworld.hex @ 96950ns | [JTAG] Writing to memory @10000000 @ 106150ns | [JTAG] Writing to memory @1000000c @ 119950ns | [JTAG] Writing to memory @10000020 @ 1401050ns | [CORE] Waking core via CLINT msip @ 1401050ns | [JTAG] Writing 0x00000001 to 0x02040000 @ 1424100ns | [JTAG] Halting hart 0... @ 1437450ns | [JTAG] Halted @ 1439750ns | [JTAG] Resumed hart 0 @ 1439750ns | [CORE] Wait for end of code... @ 3663850ns | [UART] Hello World from Croc! @ 3663850ns | [UART] raw: '{'h48, 'h65, 'h6c, 'h6c, 'h6f, 'h20, 'h57, 'h6f, 'h72, 'h6c, 'h64, 'h20, 'h66, 'h72, 'h6f, 'h6d, 'h20, 'h43, 'h72, 'h6f, 'h63, 'h21, 'ha} @ 3688800ns | [JTAG] Simulation finished: SUCCESS - ../rtl/test/croc_vip.sv:278: Verilog $finish - S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02 - Verilator: $finish at 4ms; walltime 3.344 s; speed 1.103 ms/s - Verilator: cpu 3.344 s on 1 threads; alloced 57 MB [INFO][ENV] Croc root: /fosic/designs/croc [INFO][ENV] PDK root: /fosic/designs/croc/technology [INFO][ENV] Croc PDK: sg13cmos5l [INFO][ENV] Active technology view: public mirror [INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout [INFO][ENV] Bender PDK args: -D IHP_SG13CMOS5L=1 [INFO][ENV] Tech LEF: sg13cmos5l_tech.lef [INFO][ENV] IO LEF/GDS: sg13cmos5l_io.lef/sg13cmos5l_io.gds [INFO][ENV] IO Liberty tt/ff: sg13cmos5l_io_typ_1p2V_3p3V_25C.lib/sg13cmos5l_io_fast_1p32V_3p6V_m40C.lib [INFO][ENV] Bondpad LEF/GDS: bondpad5l_70x70.lef/bondpad5l_70x70.gds [INFO][Verilator] Run Yosys-netlist simulation Running program: ../sw/bin/test/print_config.hex -Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace ClkFrequency: 20MHz UartRealBaudRate: 113636 @ 42100ns | [JTAG] Initialization success @ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000 @ 94650ns | [JTAG] Read 0x12345678 from 0x10000000 @ 94650ns | [JTAG] Read back correct data @ 94650ns | [JTAG] Loading binary from ../sw/bin/test/print_config.hex @ 96950ns | [JTAG] Writing to memory @10000000 @ 106150ns | [JTAG] Writing to memory @1000000c @ 119950ns | [JTAG] Writing to memory @10000020 @ 1923150ns | [JTAG] Writing to memory @10000c5c @ 1930050ns | [CORE] Waking core via CLINT msip @ 1930050ns | [JTAG] Writing 0x00000001 to 0x02040000 @ 1953100ns | [JTAG] Halting hart 0... @ 1966450ns | [JTAG] Halted @ 1968750ns | [JTAG] Resumed hart 0 @ 1968750ns | [CORE] Wait for end of code... @ 4484450ns | [UART] Hello World from Croc v2! @ 4484450ns | [UART] raw: '{'h48, 'h65, 'h6c, 'h6c, 'h6f, 'h20, 'h57, 'h6f, 'h72, 'h6c, 'h64, 'h20, 'h66, 'h72, 'h6f, 'h6d, 'h20, 'h43, 'h72, 'h6f, 'h63, 'h20, 'h76, 'h32, 'h21, 'ha} @ 6033250ns | [UART] iDMAEnable: 0 @ 6033250ns | [UART] raw: '{'h20, 'h20, 'h69, 'h44, 'h4d, 'h41, 'h45, 'h6e, 'h61, 'h62, 'h6c, 'h65, 'h3a, 'h20, 'h30, 'ha} @ 8162850ns | [UART] Core: CVE2, RV32CIU @ 8162850ns | [UART] raw: '{'h20, 'h20, 'h43, 'h6f, 'h72, 'h65, 'h3a, 'h20, 'h43, 'h56, 'h45, 'h32, 'h2c, 'h20, 'h52, 'h56, 'h33, 'h32, 'h43, 'h49, 'h55, 'ha} @ 9614850ns | [UART] PMPEnable: 0 @ 9614850ns | [UART] raw: '{'h20, 'h20, 'h50, 'h4d, 'h50, 'h45, 'h6e, 'h61, 'h62, 'h6c, 'h65, 'h3a, 'h20, 'h30, 'ha} @ 12518850ns | [UART] SRAM: 2h banks x 200h words @ 12518850ns | [UART] raw: '{'h20, 'h20, 'h53, 'h52, 'h41, 'h4d, 'h3a, 'h20, 'h32, 'h68, 'h20, 'h62, 'h61, 'h6e, 'h6b, 'h73, 'h20, 'h78, 'h20, 'h32, 'h30, 'h30, 'h68, 'h20, 'h77, 'h6f, 'h72, 'h64, 'h73, 'ha} @ 13777250ns | [UART] Peripherals: @ 13777250ns | [UART] raw: '{'h50, 'h65, 'h72, 'h69, 'h70, 'h68, 'h65, 'h72, 'h61, 'h6c, 'h73, 'h3a, 'ha} @ 15713250ns | [UART] Debug : present @ 15713250ns | [UART] raw: '{'h20, 'h20, 'h44, 'h65, 'h62, 'h75, 'h67, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 17649250ns | [UART] Bootrom : present @ 17649250ns | [UART] raw: '{'h20, 'h20, 'h42, 'h6f, 'h6f, 'h74, 'h72, 'h6f, 'h6d, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 19585250ns | [UART] CLINT : present @ 19585250ns | [UART] raw: '{'h20, 'h20, 'h43, 'h4c, 'h49, 'h4e, 'h54, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 21521250ns | [UART] SoC Ctrl: present @ 21521250ns | [UART] raw: '{'h20, 'h20, 'h53, 'h6f, 'h43, 'h20, 'h43, 'h74, 'h72, 'h6c, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 23457250ns | [UART] UART : present @ 23457250ns | [UART] raw: '{'h20, 'h20, 'h55, 'h41, 'h52, 'h54, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 25393250ns | [UART] GPIO : present @ 25393250ns | [UART] raw: '{'h20, 'h20, 'h47, 'h50, 'h49, 'h4f, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 27329250ns | [UART] Timer : present @ 27329250ns | [UART] raw: '{'h20, 'h20, 'h54, 'h69, 'h6d, 'h65, 'h72, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 29652450ns | [UART] iDMA : not present @ 29652450ns | [UART] raw: '{'h20, 'h20, 'h69, 'h44, 'h4d, 'h41, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h6e, 'h6f, 'h74, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 31975650ns | [UART] User ROM: not present @ 31975650ns | [UART] raw: '{'h20, 'h20, 'h55, 'h73, 'h65, 'h72, 'h20, 'h52, 'h4f, 'h4d, 'h3a, 'h20, 'h6e, 'h6f, 'h74, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 32006650ns | [JTAG] Simulation finished: SUCCESS - ../rtl/test/croc_vip.sv:278: Verilog $finish - S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02 - Verilator: $finish at 32ms; walltime 30.186 s; speed 1.060 ms/s - Verilator: cpu 30.182 s on 1 threads; alloced 57 MB Hello world simulation passed. ============================================= Phase 2: iDMA enabled — unit tests ============================================= [INFO][ENV] Croc root: /fosic/designs/croc [INFO][ENV] PDK root: /fosic/designs/croc/technology [INFO][ENV] Croc PDK: sg13cmos5l [INFO][ENV] Active technology view: public mirror [INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout [INFO][ENV] Bender PDK args: -D IHP_SG13CMOS5L=1 [INFO][ENV] Tech LEF: sg13cmos5l_tech.lef [INFO][ENV] IO LEF/GDS: sg13cmos5l_io.lef/sg13cmos5l_io.gds [INFO][ENV] IO Liberty tt/ff: sg13cmos5l_io_typ_1p2V_3p3V_25C.lib/sg13cmos5l_io_fast_1p32V_3p6V_m40C.lib [INFO][ENV] Bondpad LEF/GDS: bondpad5l_70x70.lef/bondpad5l_70x70.gds [INFO][Bender] Generate croc_netlist_yosys.f warning: [W03] Ignoring unknown field `pass_targets` in a dependency in manifest for croc_soc. [INFO][Bender] Remove absolute paths [INFO][Bender] File list generated: croc_netlist_yosys.f [INFO][Verilator] Build Yosys-netlist simulation %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:43:39: Ignoring unsupported: specify block construct 43 | (posedge A1 => (X : A1)) = (0.0,0.0); | ^ ... For warning description see https://verilator.org/warn/SPECIFYIGN?v=5.042 ... Use "/* verilator lint_off SPECIFYIGN */" and lint_on around source to disable this message. %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:104:39: Ignoring unsupported: specify block construct 104 | (posedge A1 => (X : A1)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:165:38: Ignoring unsupported: specify block construct 165 | (posedge A1 => (Y : A1)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:215:38: Ignoring unsupported: specify block construct 215 | (posedge A1 => (Y : A1)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:267:39: Ignoring unsupported: specify block construct 267 | (posedge A1 => (Y : A1)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:386:39: Ignoring unsupported: specify block construct 386 | (posedge A1 => (Y : A1)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:451:36: Ignoring unsupported: specify block construct 451 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:481:36: Ignoring unsupported: specify block construct 481 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:511:36: Ignoring unsupported: specify block construct 511 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:543:36: Ignoring unsupported: specify block construct 543 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:575:36: Ignoring unsupported: specify block construct 575 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:609:36: Ignoring unsupported: specify block construct 609 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:663:36: Ignoring unsupported: specify block construct 663 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:691:36: Ignoring unsupported: specify block construct 691 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:719:36: Ignoring unsupported: specify block construct 719 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:747:36: Ignoring unsupported: specify block construct 747 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:775:36: Ignoring unsupported: specify block construct 775 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:870:44: Ignoring unsupported: specify block construct 870 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:937:44: Ignoring unsupported: specify block construct 937 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1001:44: Ignoring unsupported: specify block construct 1001 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1062:44: Ignoring unsupported: specify block construct 1062 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1117:36: Ignoring unsupported: specify block construct 1117 | (posedge D => (Q : D)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1176:36: Ignoring unsupported: specify block construct 1176 | (posedge D => (Q : D)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1242:36: Ignoring unsupported: specify block construct 1242 | (posedge D => (Q : D)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1308:36: Ignoring unsupported: specify block construct 1308 | (posedge D => (Q : D)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1376:36: Ignoring unsupported: specify block construct 1376 | (posedge D => (Q : D)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1414:36: Ignoring unsupported: specify block construct 1414 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1443:36: Ignoring unsupported: specify block construct 1443 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1472:36: Ignoring unsupported: specify block construct 1472 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1501:36: Ignoring unsupported: specify block construct 1501 | (posedge A => (Z : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1532:36: Ignoring unsupported: specify block construct 1532 | (posedge A => (Z : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1563:36: Ignoring unsupported: specify block construct 1563 | (posedge A => (Z : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1594:36: Ignoring unsupported: specify block construct 1594 | (posedge A => (Z : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1625:36: Ignoring unsupported: specify block construct 1625 | (posedge A => (Z : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1656:36: Ignoring unsupported: specify block construct 1656 | (posedge A => (Z : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1767:36: Ignoring unsupported: specify block construct 1767 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1796:36: Ignoring unsupported: specify block construct 1796 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1825:36: Ignoring unsupported: specify block construct 1825 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1854:36: Ignoring unsupported: specify block construct 1854 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1883:36: Ignoring unsupported: specify block construct 1883 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1934:42: Ignoring unsupported: specify block construct 1934 | (posedge CLK => (GCLK :CLK)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:1967:38: Ignoring unsupported: specify block construct 1967 | (posedge A0 => (X : A0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2011:38: Ignoring unsupported: specify block construct 2011 | (posedge A0 => (X : A0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2054:38: Ignoring unsupported: specify block construct 2054 | (posedge A0 => (X : A0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2132:36: Ignoring unsupported: specify block construct 2132 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2166:36: Ignoring unsupported: specify block construct 2166 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2201:40: Ignoring unsupported: specify block construct 2201 | (posedge A_N => (Y : A_N)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2236:40: Ignoring unsupported: specify block construct 2236 | (posedge A_N => (Y : A_N)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2270:36: Ignoring unsupported: specify block construct 2270 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2307:40: Ignoring unsupported: specify block construct 2307 | (posedge A_N => (Y : A_N)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2343:36: Ignoring unsupported: specify block construct 2343 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2381:36: Ignoring unsupported: specify block construct 2381 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2415:36: Ignoring unsupported: specify block construct 2415 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2450:36: Ignoring unsupported: specify block construct 2450 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2485:36: Ignoring unsupported: specify block construct 2485 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2519:36: Ignoring unsupported: specify block construct 2519 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2555:36: Ignoring unsupported: specify block construct 2555 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2591:36: Ignoring unsupported: specify block construct 2591 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2629:36: Ignoring unsupported: specify block construct 2629 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2668:38: Ignoring unsupported: specify block construct 2668 | (posedge A1 => (Y : A1)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2707:36: Ignoring unsupported: specify block construct 2707 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2738:36: Ignoring unsupported: specify block construct 2738 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2769:36: Ignoring unsupported: specify block construct 2769 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2802:36: Ignoring unsupported: specify block construct 2802 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2835:36: Ignoring unsupported: specify block construct 2835 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2870:36: Ignoring unsupported: specify block construct 2870 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:2939:44: Ignoring unsupported: specify block construct 2939 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3030:44: Ignoring unsupported: specify block construct 3030 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3115:44: Ignoring unsupported: specify block construct 3115 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3198:44: Ignoring unsupported: specify block construct 3198 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3277:44: Ignoring unsupported: specify block construct 3277 | (negedge RESET_B => (Q :1'b0)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3350:42: Ignoring unsupported: specify block construct 3350 | (posedge CLK => (GCLK :CLK)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3508:37: Ignoring unsupported: specify block construct 3508 | (posedge A => (Y : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/sg13g2_stdcell.v:3559:37: Ignoring unsupported: specify block construct 3559 | (posedge A => (X : A)) = (0.0,0.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct 137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct 137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_256x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct 137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_512x32_c2_bm_bist.v:138:54: Ignoring unsupported: specify block construct 138 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_512x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct 137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct 137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct 137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0); | ^ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:105228:63: Instance has missing pin: 'busy_o' 105228 | \croc_idma$croc_chip.i_croc_soc.i_croc.gen_dma.i_croc_idma \gen_dma.i_croc_idma ( | ^~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:106433:186: ... Location of port declaration 106433 | module \croc_idma$croc_chip.i_croc_soc.i_croc.gen_dma.i_croc_idma (clk_i, rst_ni, obi_cfg_req_i, obi_cfg_rsp_o, obi_read_req_o, obi_read_rsp_i, obi_write_req_o, obi_write_rsp_i, irq_o, busy_o); | ^~~~~~ ... For warning description see https://verilator.org/warn/PINMISSING?v=5.042 ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Warning-PINMISSING: ../yosys/out/netlist_debug.v:105242:70: Instance has missing pin: 'impl_o' 105242 | \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[0].i_sram \gen_sram_bank[0].i_sram ( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:285382:143: ... Location of port declaration 285382 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[0].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o); | ^~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:105263:70: Instance has missing pin: 'impl_o' 105263 | \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[1].i_sram \gen_sram_bank[1].i_sram ( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:285453:143: ... Location of port declaration 285453 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[1].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o); | ^~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:105380:53: Instance has missing pin: 'tdo_oe_o' 105380 | \dmi_jtag$croc_chip.i_croc_soc.i_croc.i_dmi_jtag i_dmi_jtag ( | ^~~~~~~~~~ ../yosys/out/netlist_debug.v:242356:225: ... Location of port declaration 242356 | module \dmi_jtag$croc_chip.i_croc_soc.i_croc.i_dmi_jtag (clk_i, rst_ni, testmode_i, dmi_rst_no, dmi_req_o, dmi_req_valid_o, dmi_req_ready_i, dmi_resp_i, dmi_resp_ready_o, dmi_resp_valid_i, tck_i, tms_i, trst_ni, td_i, td_o, tdo_oe_o); | ^~~~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:106366:55: Instance has missing pin: 'overflow_o' 106366 | \obi_timer$croc_chip.i_croc_soc.i_croc.i_obi_timer i_obi_timer ( | ^~~~~~~~~~~ ../yosys/out/netlist_debug.v:259869:108: ... Location of port declaration 259869 | module \obi_timer$croc_chip.i_croc_soc.i_croc.i_obi_timer (clk_i, rst_ni, obi_req_i, obi_rsp_o, expired_o, overflow_o); | ^~~~~~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:106401:49: Instance has missing pin: 'irq_no' 106401 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart ( | ^~~~~~ ../yosys/out/netlist_debug.v:264371:142: ... Location of port declaration 264371 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, irq_o, obi_req_i, obi_rsp_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no); | ^~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:106401:49: Instance has missing pin: 'rts_no' 106401 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart ( | ^~~~~~ ../yosys/out/netlist_debug.v:264371:150: ... Location of port declaration 264371 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, irq_o, obi_req_i, obi_rsp_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no); | ^~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:106401:49: Instance has missing pin: 'dtr_no' 106401 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart ( | ^~~~~~ ../yosys/out/netlist_debug.v:264371:158: ... Location of port declaration 264371 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, irq_o, obi_req_i, obi_rsp_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no); | ^~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:106401:49: Instance has missing pin: 'out1_no' 106401 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart ( | ^~~~~~ ../yosys/out/netlist_debug.v:264371:166: ... Location of port declaration 264371 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, irq_o, obi_req_i, obi_rsp_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no); | ^~~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:106401:49: Instance has missing pin: 'out2_no' 106401 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart ( | ^~~~~~ ../yosys/out/netlist_debug.v:264371:175: ... Location of port declaration 264371 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, irq_o, obi_req_i, obi_rsp_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no); | ^~~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:249391:85: Instance has missing pin: 'src_clear_pending_o' 249391 | \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req \i_dmi_cdc.i_cdc_req ( | ^~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:2725:259: ... Location of port declaration 2725 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o); | ^~~~~~~~~~~~~~~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:249409:86: Instance has missing pin: 'dst_clear_pending_o' 249409 | \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp \i_dmi_cdc.i_cdc_resp ( | ^~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:3080:201: ... Location of port declaration 3080 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o); | ^~~~~~~~~~~~~~~~~~~ %Warning-PINMISSING: ../yosys/out/netlist_debug.v:249409:86: Instance has missing pin: 'src_clear_pending_o' 249409 | \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp \i_dmi_cdc.i_cdc_resp ( | ^~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:3080:260: ... Location of port declaration 3080 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o); | ^~~~~~~~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_verification/clk_rst_gen.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module clk_rst_gen #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.042 ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_sram.sv:56:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 56 | module tc_sram #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_sram_impl.sv:27:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 27 | module tc_sram_impl #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module tc_clk_and2 ( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:21:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 21 | module tc_clk_buffer ( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 31 | module tc_clk_gating #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:56:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 56 | module tc_clk_inverter ( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:75:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 75 | module tc_clk_mux2 ( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:86:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 86 | module tc_clk_xor2 ( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:96:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 96 | module tc_clk_or2 ( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 107 | module tc_clk_delay #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/binary_to_gray.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module binary_to_gray #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cb_filter_pkg.sv:14:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 14 | package cb_filter_pkg; | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cc_onehot.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module cc_onehot #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_reset_ctrlr_pkg.sv:18:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | package cdc_reset_ctrlr_pkg; | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cf_math_pkg.sv:18:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | package cf_math_pkg; | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/clk_int_div.sv:70:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 70 | module clk_int_div #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/credit_counter.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module credit_counter #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/delta_counter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module delta_counter #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/ecc_pkg.sv:15:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | package ecc_pkg; | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/edge_propagator_tx.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module edge_propagator_tx ( | ^~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/exp_backoff.sv:25:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 25 | module exp_backoff #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/fifo_v3.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module fifo_v3 #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/gray_to_binary.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module gray_to_binary #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/heaviside.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module heaviside #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/isochronous_4phase_handshake.sv:44:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 44 | module isochronous_4phase_handshake ( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/isochronous_spill_register.sv:41:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 41 | module isochronous_spill_register #( | ^~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/lfsr.sv:24:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 24 | module lfsr #( | ^~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/lfsr_16bit.sv:23:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 23 | module lfsr_16bit #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/lfsr_8bit.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module lfsr_8bit #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/lossy_valid_to_stream.sv:49:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 49 | module lossy_valid_to_stream #( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/mv_filter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module mv_filter #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/onehot_to_bin.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module onehot_to_bin #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/plru_tree.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module plru_tree #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/passthrough_stream_fifo.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module passthrough_stream_fifo #( | ^~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/popcount.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 22 | module popcount #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/ring_buffer.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 22 | module ring_buffer #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/rr_arb_tree.sv:49:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 49 | module rr_arb_tree #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/rstgen_bypass.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module rstgen_bypass #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/serial_deglitch.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module serial_deglitch #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/shift_reg.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module shift_reg #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/shift_reg_gated.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module shift_reg_gated #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/spill_register_flushable.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module spill_register_flushable #( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_demux.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module stream_demux #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_filter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module stream_filter ( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fork.sv:21:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 21 | module stream_fork #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_join_dynamic.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 20 | module stream_join_dynamic #( | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_mux.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module stream_mux #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_throttle.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module stream_throttle #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/sub_per_hash.sv:39:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 39 | module sub_per_hash #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/sync.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module sync #( | ^~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/sync_wedge.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module sync_wedge #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/unread.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module unread ( | ^~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/read.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module read #( | ^~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/addr_decode_dync.sv:40:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 40 | module addr_decode_dync #( | ^~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/boxcar.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module boxcar #( | ^~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase.sv:43:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 43 | module cdc_2phase #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase.sv:92:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 92 | module cdc_2phase_src #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase.sv:142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 142 | module cdc_2phase_dst #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_4phase.sv:36:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 36 | module cdc_4phase #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_4phase.sv:92:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 92 | module cdc_4phase_src #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_4phase.sv:205:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 205 | module cdc_4phase_dst #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/clk_int_div_static.sv:60:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 60 | module clk_int_div_static #( | ^~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/trip_counter.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module trip_counter #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/addr_decode.sv:35:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 35 | module addr_decode #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/addr_decode_napot.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module addr_decode_napot #( | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/multiaddr_decode.sv:32:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 32 | module multiaddr_decode #( | ^~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cb_filter.sv:45:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 45 | module cb_filter #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cb_filter.sv:203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 203 | module hash_block #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_2phase.sv:47:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 47 | module cdc_fifo_2phase #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/clk_mux_glitch_free.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 73 | module clk_mux_glitch_free #( | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/clk_mux_glitch_free.sv:256:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 256 | module clk_or_tree #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/counter.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 14 | module counter #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/ecc_decode.sv:29:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 29 | module ecc_decode import ecc_pkg::*; #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/ecc_encode.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 22 | module ecc_encode import ecc_pkg::*; #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/edge_detect.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 14 | module edge_detect ( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/lzc.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module lzc #( | ^~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/max_counter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module max_counter #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/rstgen.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module rstgen ( | ^~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/spill_register.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module spill_register #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_delay.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 14 | module stream_delay #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fifo.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module stream_fifo #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fork_dynamic.sv:24:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 24 | module stream_fork_dynamic #( | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_join.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module stream_join #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_reset_ctrlr.sv:109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 109 | module cdc_reset_ctrlr | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_reset_ctrlr.sv:187:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 187 | module cdc_reset_ctrlr_half | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 103 | module cdc_fifo_gray #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray.sv:171:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 171 | module cdc_fifo_gray_src #( | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray.sv:231:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 231 | module cdc_fifo_gray_dst #( | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/fall_through_register.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module fall_through_register #( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/id_queue.sv:50:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 50 | module id_queue #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_to_mem.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module stream_to_mem #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_arbiter_flushable.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module stream_arbiter_flushable #( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fifo_optimal_wrap.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module stream_fifo_optimal_wrap #( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_register.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module stream_register #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_xbar.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module stream_xbar #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray_clearable.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 103 | module cdc_fifo_gray_clearable #( | ^~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray_clearable.sv:268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 268 | module cdc_fifo_gray_src_clearable #( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray_clearable.sv:328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 328 | module cdc_fifo_gray_dst_clearable #( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase_clearable.sv:54:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 54 | module cdc_2phase_clearable #( | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase_clearable.sv:199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 199 | module cdc_2phase_src_clearable #( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase_clearable.sv:269:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 269 | module cdc_2phase_dst_clearable #( | ^~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/mem_to_banks_detailed.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module mem_to_banks_detailed #( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_arbiter.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module stream_arbiter #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/stream_omega_net.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 20 | module stream_omega_net #( | ^~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/common_cells/mem_to_banks.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module mem_to_banks #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_pkg.sv:7:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | package obi_pkg; | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_rready_converter.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | module obi_rready_converter #( | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/apb_to_obi.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module apb_to_obi #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_to_apb.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module obi_to_apb #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_atop_resolver.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module obi_atop_resolver | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_atop_resolver.sv:536:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 536 | module obi_atop_resolver_intf | ^~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_cut.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | module obi_cut #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_demux.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | module obi_demux #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_demux.sv:114:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 114 | module obi_demux_intf #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_err_sbr.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | module obi_err_sbr #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_err_sbr.sv:69:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 69 | module obi_err_sbr_intf #( | ^~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_mux.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module obi_mux #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_mux.sv:166:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 166 | module obi_mux_intf #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_sram_shim.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | module obi_sram_shim #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_xbar.sv:8:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8 | module obi_xbar #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi/obi_xbar.sv:161:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 161 | module obi_xbar_intf #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/apb/apb_pkg.sv:15:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | package apb_pkg; | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_pkg.sv:10:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | package cve2_pkg; | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_alu.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module cve2_alu #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_branch_predict.sv:21:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 21 | module cve2_branch_predict ( | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_compressed_decoder.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module cve2_compressed_decoder ( | ^~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_controller.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module cve2_controller #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_counter.sv:6:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 6 | module cve2_counter #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_csr.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module cve2_csr #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_decoder.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module cve2_decoder #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_fetch_fifo.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module cve2_fetch_fifo #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_load_store_unit.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module cve2_load_store_unit | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_multdiv_fast.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module cve2_multdiv_fast #( | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_multdiv_slow.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module cve2_multdiv_slow | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_pmp.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9 | module cve2_pmp #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_register_file_ff.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 14 | module cve2_register_file_ff #( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_wb.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module cve2_wb #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_cs_registers.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module cve2_cs_registers #( | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_ex_block.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module cve2_ex_block #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_id_stage.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 20 | module cve2_id_stage #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_prefetch_buffer.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module cve2_prefetch_buffer #( | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_if_stage.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module cve2_if_stage import cve2_pkg::*; ( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/cve2/cve2_core.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 16 | module cve2_core import cve2_pkg::*; #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_pkg.sv:11:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | package idma_pkg; | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_channel_coupler.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module idma_channel_coupler #( | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_dataflow_element.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module idma_dataflow_element #( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_obi_read.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module idma_obi_read #( | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_obi_write.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | module idma_obi_write #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_nd_midend.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module idma_nd_midend #( | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_nd_midend.sv:252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 252 | module idma_nd_counter #( | ^~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_transfer_id_gen.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9 | module idma_transfer_id_gen #( | ^~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_legalizer_page_splitter.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9 | module idma_legalizer_page_splitter #( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_transport_layer_rw_obi.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 13 | module idma_transport_layer_rw_obi #( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_legalizer_rw_obi.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 15 | module idma_legalizer_rw_obi #( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/idma_backend_rw_obi.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module idma_backend_rw_obi #( | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/idma/croc_idma.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module croc_idma #( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_pkg.sv:9:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9 | package obi_uart_pkg; | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_baudgen.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module obi_uart_baudgen import obi_uart_pkg::*; #() | ^~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_interrupts.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module obi_uart_interrupts import obi_uart_pkg::*; #() | ^~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_modem.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | module obi_uart_modem import obi_uart_pkg::*; #() | ^~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_rx.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module obi_uart_rx import obi_uart_pkg::*; #() | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_tx.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module obi_uart_tx #() | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_register.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module obi_uart_register import obi_uart_pkg::*; #( | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module obi_uart #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_pkg.sv:19:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | package dm; | ^~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/debug_rom/debug_rom.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module debug_rom ( | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 17 | module debug_rom_one_scratch ( | ^~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_csrs.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module dm_csrs #( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_mem.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module dm_mem #( | ^~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dmi_cdc.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module dmi_cdc ( | ^~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dmi_jtag_tap.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module dmi_jtag_tap #( | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_sba.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18 | module dm_sba #( | ^~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_top.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 20 | module dm_top #( | ^~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dmi_jtag.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 19 | module dmi_jtag #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_obi_top.sv:63:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 63 | module dm_obi_top #( | ^~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/tb/jtag_test_simple.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module jtag_driver_simple #( | ^~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/riscv-dbg/tb/jtag_test_simple.sv:163:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 163 | module riscv_dbg_simple #( | ^~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/croc_pkg.sv:12:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12 | package croc_pkg; | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/user_pkg.sv:10:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | package user_pkg; | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/soc_ctrl/soc_ctrl_regs_pkg.sv:8:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8 | package soc_ctrl_regs_pkg; | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/gpio/gpio_reg_pkg.sv:10:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10 | package gpio_reg_pkg; | ^~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/clint/clint_reg_pkg.sv:8:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8 | package clint_reg_pkg; | ^~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/obi_timer/obi_timer_reg_pkg.sv:8:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8 | package obi_timer_reg_pkg; | ^~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:4:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 4 | module \bootrom$croc_chip.i_croc_soc.i_croc.i_bootrom (clk_i, rst_ni, obi_req_i, obi_rsp_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:2725:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 2725 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:3080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 3080 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:3407:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 3407 | module \cdc_2phase_dst_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_dst (clk_i, rst_ni, data_o, valid_o, ready_i, clear_i, async_req_i, async_ack_o, async_data_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:4736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 4736 | module \cdc_2phase_dst_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_dst (clk_i, rst_ni, data_o, valid_o, ready_i, clear_i, async_req_i, async_ack_o, async_data_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:5864:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 5864 | module \cdc_2phase_src_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_src (clk_i, rst_ni, data_i, valid_i, ready_o, clear_i, async_req_o, async_ack_i, async_data_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:7170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7170 | module \cdc_2phase_src_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_src (clk_i, rst_ni, data_i, valid_i, ready_o, clear_i, async_req_o, async_ack_i, async_data_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:8275:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8275 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, valid_o, ready_i, async_req_i, async_ack_o, async_data_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:8418:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8418 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, valid_o, ready_i, async_req_i, async_ack_o, async_data_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:8561:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8561 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, valid_o, ready_i, async_req_i, async_ack_o, async_data_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:8704:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8704 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, valid_o, ready_i, async_req_i, async_ack_o, async_data_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:8847:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 8847 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9066:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9066 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9285:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9285 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9504:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9504 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9723:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9723 | module \cdc_reset_ctrlr$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr (a_clk_i, a_rst_ni, a_clear_i, a_clear_o, a_clear_ack_i, a_isolate_o, a_isolate_ack_i, b_clk_i, b_rst_ni, b_clear_i, b_clear_o, b_clear_ack_i, b_isolate_o, b_isolate_ack_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9853:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9853 | module \cdc_reset_ctrlr$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr (a_clk_i, a_rst_ni, a_clear_i, a_clear_o, a_clear_ack_i, a_isolate_o, a_isolate_ack_i, b_clk_i, b_rst_ni, b_clear_i, b_clear_o, b_clear_ack_i, b_isolate_o, b_isolate_ack_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9983:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9983 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:10603:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 10603 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11223 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11848:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11848 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:12468:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 12468 | module \clint$croc_chip.i_croc_soc.i_croc.i_clint (clk_i, rst_ni, obi_req_i, obi_rsp_o, rtc_i, software_irq_o, timer_irq_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:18834:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 18834 | module \core_wrap$croc_chip.i_croc_soc.i_croc.i_core_wrap (clk_i, rst_ni, core_busy_o, test_enable_i, irqs_i, timer_irq_i, software_irq_i, boot_addr_i, instr_req_o, instr_gnt_i, instr_rvalid_i, instr_addr_o, instr_rdata_i, instr_err_i, data_req_o, data_gnt_i, data_rvalid_i, data_we_o, data_be_o, data_addr_o, data_wdata_o | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:57642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 57642 | module croc_chip(clk_i, rst_ni, ref_clk_i, jtag_tck_i, jtag_trst_ni, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, uart_rx_i, uart_tx_o, testmode_i, status_o, gpio0_io, gpio1_io, gpio2_io, gpio3_io, gpio4_io, gpio5_io, gpio6_io, gpio7_io, gpio8_io | ^~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:58632:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 58632 | module \croc_domain$croc_chip.i_croc_soc.i_croc (clk_i, rst_ni, ref_clk_i, jtag_tck_i, jtag_trst_ni, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, uart_rx_i, uart_tx_o, testmode_i, gpio_i, gpio_o, gpio_out_en_o, gpio_in_sync_o, user_sbr_obi_req_o, user_sbr_obi_rsp_i, user_mgr_obi_req_i, user_mgr_obi_rsp_o, interrupts_i, core_busy_o | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:106433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 106433 | module \croc_idma$croc_chip.i_croc_soc.i_croc.gen_dma.i_croc_idma (clk_i, rst_ni, obi_cfg_req_i, obi_cfg_rsp_o, obi_read_req_o, obi_read_rsp_i, obi_write_req_o, obi_write_rsp_i, irq_o, busy_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:152871:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 152871 | module \croc_soc$croc_chip.i_croc_soc (clk_i, rst_ni, ref_clk_i, jtag_tck_i, jtag_trst_ni, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, uart_rx_i, uart_tx_o, testmode_i, status_o, gpio_i, gpio_o, gpio_out_en_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:153833:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 153833 | module \cve2_cs_registers$croc_chip.i_croc_soc.i_croc.i_core_wrap.i_core.cs_registers_i (clk_i, rst_ni, boot_addr_i, hart_id_i, irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_pending_o, pc_id_i, priv_mode_id_o, priv_mode_lsu_o, csr_mstatus_tw_o, csr_mtvec_o, csr_mtvec_init_i, csr_access_i, csr_addr_i, csr_wdata_i, csr_op_i, csr_op_en_i, csr_rdata_o | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:177608:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 177608 | module \cve2_register_file_ff$croc_chip.i_croc_soc.i_croc.i_core_wrap.i_core.register_file_i (clk_i, rst_ni, test_en_i, raddr_a_i, rdata_a_o, raddr_b_i, rdata_b_o, waddr_a_i, wdata_a_i, we_a_i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:208477:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 208477 | module \dm_top$croc_chip.i_croc_soc.i_croc.i_dm_top.i_dm_top (clk_i, rst_ni, testmode_i, debug_req_o, unavailable_i, hartinfo_i, slave_req_i, slave_we_i, slave_addr_i, slave_be_i, slave_wdata_i, slave_rdata_o, master_req_o, master_we_o, master_wdata_o, master_be_o, master_gnt_i, dmi_rst_ni, dmi_req_valid_i, dmi_req_ready_o, dmi_req_i | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:242356:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 242356 | module \dmi_jtag$croc_chip.i_croc_soc.i_croc.i_dmi_jtag (clk_i, rst_ni, testmode_i, dmi_rst_no, dmi_req_o, dmi_req_valid_o, dmi_req_ready_i, dmi_resp_i, dmi_resp_ready_o, dmi_resp_valid_i, tck_i, tms_i, trst_ni, td_i, td_o, tdo_oe_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:249820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 249820 | module \gpio$croc_chip.i_croc_soc.i_croc.i_gpio (clk_i, rst_ni, gpio_i, gpio_o, gpio_out_en_o, gpio_in_sync_o, obi_req_i, obi_rsp_o, interrupt_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:259869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 259869 | module \obi_timer$croc_chip.i_croc_soc.i_croc.i_obi_timer (clk_i, rst_ni, obi_req_i, obi_rsp_o, expired_o, overflow_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:264371:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 264371 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, irq_o, obi_req_i, obi_rsp_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:280154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 280154 | module \soc_ctrl_regs$croc_chip.i_croc_soc.i_croc.i_soc_ctrl (clk_i, rst_ni, obi_req_i, obi_rsp_o, fetch_en_o, sram_dly_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283053:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283053 | module \sync$croc_chip.i_croc_soc.i_croc.i_clint.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283096:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283096 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283139 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283182:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283182 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283225:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283225 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283268 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_dst.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283322:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283322 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_src.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283376:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283376 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283419 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283462:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283462 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283505:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283505 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283548:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283548 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_dst.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283602:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283602 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_src.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283656 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[0].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283699 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[10].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283742:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283742 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[11].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283785 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[12].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283828 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[13].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283871:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283871 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[14].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283914 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[15].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:283957:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 283957 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[16].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284000 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[17].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284043:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284043 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[18].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284086 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[19].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284129 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[1].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284172:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284172 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[20].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284215 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[21].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284258 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[22].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284301 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[23].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284344:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284344 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[24].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284387:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284387 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[25].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284430:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284430 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[26].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284473:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284473 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[27].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284516:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284516 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[28].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284559 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[29].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284602:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284602 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[2].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284645:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284645 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[30].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284688 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[31].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284731 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[3].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284774:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284774 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[4].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284817 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[5].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284860 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[6].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284903:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284903 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[7].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284946:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284946 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[8].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:284989:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 284989 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[9].i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285032:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285032 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_cd (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285075:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285075 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_cts (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285118 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_dsr (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285161:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285161 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_ri (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285204:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285204 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_rx.i_sync (clk_i, rst_ni, serial_i, serial_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285247:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285247 | module \tc_clk_inverter$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_jtag_tap.i_tck_inv (clk_i, clk_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285266:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285266 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_jtag_tap.i_dft_tck_mux (clk0_i, clk1_i, clk_sel_i, clk_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285295:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285295 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_rstgen.i_rstgen_bypass.i_tc_clk_mux2_init_no (clk0_i, clk1_i, clk_sel_i, clk_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285324:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285324 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_rstgen.i_rstgen_bypass.i_tc_clk_mux2_rst_n (clk0_i, clk1_i, clk_sel_i, clk_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285353:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285353 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_rstgen.i_rstgen_bypass.i_tc_clk_mux2_rst_no (clk0_i, clk1_i, clk_sel_i, clk_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285382:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285382 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[0].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285453:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285453 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[1].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:285524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 285524 | module \user_domain$croc_chip.i_croc_soc.i_user (clk_i, rst_ni, ref_clk_i, testmode_i, user_sbr_obi_req_i, user_sbr_obi_rsp_o, user_mgr_obi_req_o, user_mgr_obi_rsp_i, gpio_in_sync_i, interrupts_o); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/test/tb_croc_pkg.sv:9:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9 | package tb_croc_pkg; | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/test/croc_vip.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 9 | module croc_vip #( | ^~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-TIMESCALEMOD: ../rtl/test/tb_croc_soc.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 11 | module tb_croc_soc #( | ^~~~~~~~~~~ ../technology/verilog/sg13g2_stdcell.v:28:8: ... Location of module with timescale 28 | module sg13g2_a21o_1 (X, A1, A2, B1); | ^~~~~~~~~~~~~ %Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:61845:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5726' 61845 | wire \$abc$199608$new_n5726 ; | ^~~~~~~~~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=5.042 ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. ../yosys/out/netlist_debug.v:61845:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5726 ../technology/verilog/sg13g2_stdcell.v:380:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61850:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5732 ../technology/verilog/sg13g2_stdcell.v:476:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:285590:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$225802$new_n119 ../yosys/out/netlist_debug.v:286236:64: Example path: ASSIGNW ../yosys/out/netlist_debug.v:285547:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o ../technology/verilog/sg13g2_stdcell.v:2376:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2146 ../technology/verilog/sg13g2_stdcell.v:506:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59179:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2341 ../technology/verilog/sg13g2_stdcell.v:446:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59369:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2534 ../yosys/out/netlist_debug.v:59364:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59364:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2529 ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:59476:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2643 ../yosys/out/netlist_debug.v:59518:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59518:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2685 ../yosys/out/netlist_debug.v:61886:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61886:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5768 ../yosys/out/netlist_debug.v:61887:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61887:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5769 ../yosys/out/netlist_debug.v:62665:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62665:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n6671 ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__gen_dma.i_croc_idma__obi_write_rsp_i ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.obi_write_rsp_i ../yosys/out/netlist_debug.v:107984:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107984:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3077 ../yosys/out/netlist_debug.v:107985:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3078 ../technology/verilog/sg13g2_stdcell.v:1762:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107988:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3081 ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: ASSIGNW ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: __VdfgRegularize_he50b618e_0_1093 ../yosys/out/netlist_debug.v:152867:56: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106460:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__gen_dma.i_croc_idma__obi_write_req_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:58907:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2068 ../yosys/out/netlist_debug.v:58992:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58992:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2154 ../yosys/out/netlist_debug.v:59070:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59070:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2232 ../yosys/out/netlist_debug.v:59674:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59674:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2841 ../yosys/out/netlist_debug.v:59722:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59722:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2889 ../technology/verilog/sg13g2_stdcell.v:2127:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60566:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n3958 ../yosys/out/netlist_debug.v:64935:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264386:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__i_uart__obi_req_i ../yosys/out/netlist_debug.v:280150:47: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264390:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:61867:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5749 ../yosys/out/netlist_debug.v:61886:8: Example path: ASSIGNW %Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:60733:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n4499' 60733 | wire \$abc$199608$new_n4499 ; | ^~~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:60733:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n4499 ../technology/verilog/sg13g2_stdcell.v:2264:24: Example path: ASSIGNW ../technology/verilog/sg13g2_stdcell.v:2264:24: Example path: __VdfgRegularize_he50b618e_0_1137 ../technology/verilog/sg13g2_stdcell.v:476:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:285590:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$225802$new_n119 ../yosys/out/netlist_debug.v:286236:64: Example path: ASSIGNW ../yosys/out/netlist_debug.v:285547:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o ../technology/verilog/sg13g2_stdcell.v:2376:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2146 ../technology/verilog/sg13g2_stdcell.v:506:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59179:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2341 ../technology/verilog/sg13g2_stdcell.v:446:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59369:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2534 ../yosys/out/netlist_debug.v:59364:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59364:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2529 ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:59476:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2643 ../yosys/out/netlist_debug.v:59518:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59518:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2685 ../yosys/out/netlist_debug.v:61886:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61886:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5768 ../yosys/out/netlist_debug.v:61887:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61887:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5769 ../yosys/out/netlist_debug.v:62665:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62665:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n6671 ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__gen_dma.i_croc_idma__obi_write_rsp_i ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.obi_write_rsp_i ../yosys/out/netlist_debug.v:107984:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107984:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3077 ../yosys/out/netlist_debug.v:107985:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3078 ../technology/verilog/sg13g2_stdcell.v:1762:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107988:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3081 ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: ASSIGNW ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: __VdfgRegularize_he50b618e_0_1093 ../yosys/out/netlist_debug.v:152867:56: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106460:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__gen_dma.i_croc_idma__obi_write_req_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:58907:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2068 ../yosys/out/netlist_debug.v:58992:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58992:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2154 ../yosys/out/netlist_debug.v:59070:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59070:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2232 ../yosys/out/netlist_debug.v:59674:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59674:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2841 ../yosys/out/netlist_debug.v:59722:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59722:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2889 ../technology/verilog/sg13g2_stdcell.v:2127:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60566:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n3958 ../yosys/out/netlist_debug.v:64935:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264386:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__i_uart__obi_req_i ../yosys/out/netlist_debug.v:280150:47: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264390:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:61867:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5749 ../yosys/out/netlist_debug.v:61886:8: Example path: ASSIGNW %Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:68482:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_demux[2].i_demux.i_counter.down_i' 68482 | wire \i_main_xbar.gen_demux[2].i_demux.i_counter.down_i ; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:68482:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_demux[2].i_demux.i_counter.down_i ../yosys/out/netlist_debug.v:59700:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59700:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2867 ../yosys/out/netlist_debug.v:59709:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59709:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2876 ../technology/verilog/sg13g2_stdcell.v:2264:24: Example path: ASSIGNW ../technology/verilog/sg13g2_stdcell.v:2264:24: Example path: __VdfgRegularize_he50b618e_0_187 ../technology/verilog/sg13g2_stdcell.v:476:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:285590:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$225802$new_n119 ../yosys/out/netlist_debug.v:286236:64: Example path: ASSIGNW ../yosys/out/netlist_debug.v:285547:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o ../technology/verilog/sg13g2_stdcell.v:2376:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2146 ../technology/verilog/sg13g2_stdcell.v:506:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59179:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2341 ../technology/verilog/sg13g2_stdcell.v:446:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59369:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2534 ../yosys/out/netlist_debug.v:59364:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59364:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2529 ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:59476:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2643 ../yosys/out/netlist_debug.v:59518:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59518:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2685 ../yosys/out/netlist_debug.v:61886:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61886:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5768 ../yosys/out/netlist_debug.v:61887:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61887:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5769 ../yosys/out/netlist_debug.v:62665:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62665:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n6671 ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__gen_dma.i_croc_idma__obi_write_rsp_i ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.obi_write_rsp_i ../yosys/out/netlist_debug.v:107984:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107984:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3077 ../yosys/out/netlist_debug.v:107985:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3078 ../technology/verilog/sg13g2_stdcell.v:1762:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107988:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3081 ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: ASSIGNW ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: __VdfgRegularize_he50b618e_0_1093 ../yosys/out/netlist_debug.v:152867:56: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106460:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__gen_dma.i_croc_idma__obi_write_req_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:58907:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2068 ../yosys/out/netlist_debug.v:58992:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58992:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2154 ../yosys/out/netlist_debug.v:59070:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59070:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2232 ../yosys/out/netlist_debug.v:59674:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59674:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2841 ../yosys/out/netlist_debug.v:59722:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59722:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2889 ../technology/verilog/sg13g2_stdcell.v:2127:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60566:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n3958 ../yosys/out/netlist_debug.v:64935:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264386:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__i_uart__obi_req_i ../yosys/out/netlist_debug.v:280150:47: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264390:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:61867:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5749 ../yosys/out/netlist_debug.v:61886:8: Example path: ASSIGNW %Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:107985:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3078' 107985 | wire \$abc$205972$new_n3078 ; | ^~~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:107985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3078 ../technology/verilog/sg13g2_stdcell.v:1762:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107988:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3081 ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: ASSIGNW ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: __VdfgRegularize_he50b618e_0_1093 ../yosys/out/netlist_debug.v:152867:56: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106460:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__gen_dma.i_croc_idma__obi_write_req_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:58907:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2068 ../yosys/out/netlist_debug.v:58992:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58992:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2154 ../yosys/out/netlist_debug.v:59070:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59070:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2232 ../yosys/out/netlist_debug.v:59674:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59674:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2841 ../yosys/out/netlist_debug.v:59722:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59722:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2889 ../technology/verilog/sg13g2_stdcell.v:2127:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60566:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n3958 ../yosys/out/netlist_debug.v:64935:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264386:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__i_uart__obi_req_i ../yosys/out/netlist_debug.v:280150:47: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264390:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:61867:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5749 ../yosys/out/netlist_debug.v:61886:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61886:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5768 ../yosys/out/netlist_debug.v:61887:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61887:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5769 ../yosys/out/netlist_debug.v:62665:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62665:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n6671 ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__gen_dma.i_croc_idma__obi_write_rsp_i ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.obi_write_rsp_i ../yosys/out/netlist_debug.v:107984:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107984:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3077 ../yosys/out/netlist_debug.v:107985:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3078 %Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:61826:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5704' 61826 | wire \$abc$199608$new_n5704 ; | ^~~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:61826:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5704 ../technology/verilog/sg13g2_stdcell.v:2264:24: Example path: ASSIGNW ../technology/verilog/sg13g2_stdcell.v:2264:24: Example path: __VdfgRegularize_he50b618e_0_185 ../technology/verilog/sg13g2_stdcell.v:476:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:285590:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$225802$new_n119 ../yosys/out/netlist_debug.v:286236:64: Example path: ASSIGNW ../yosys/out/netlist_debug.v:285547:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o ../technology/verilog/sg13g2_stdcell.v:2376:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2146 ../technology/verilog/sg13g2_stdcell.v:506:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59179:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2341 ../technology/verilog/sg13g2_stdcell.v:446:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59369:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2534 ../yosys/out/netlist_debug.v:59364:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59364:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2529 ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:59476:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2643 ../yosys/out/netlist_debug.v:59518:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59518:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2685 ../yosys/out/netlist_debug.v:61886:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61886:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5768 ../yosys/out/netlist_debug.v:61887:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61887:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5769 ../yosys/out/netlist_debug.v:62665:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62665:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n6671 ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__gen_dma.i_croc_idma__obi_write_rsp_i ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.obi_write_rsp_i ../yosys/out/netlist_debug.v:107984:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107984:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3077 ../yosys/out/netlist_debug.v:107985:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3078 ../technology/verilog/sg13g2_stdcell.v:1762:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107988:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3081 ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: ASSIGNW ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: __VdfgRegularize_he50b618e_0_1093 ../yosys/out/netlist_debug.v:152867:56: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106460:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__gen_dma.i_croc_idma__obi_write_req_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:58907:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2068 ../yosys/out/netlist_debug.v:58992:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58992:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2154 ../yosys/out/netlist_debug.v:59070:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59070:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2232 ../yosys/out/netlist_debug.v:59674:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59674:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2841 ../yosys/out/netlist_debug.v:59722:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59722:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2889 ../technology/verilog/sg13g2_stdcell.v:2127:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60566:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n3958 ../yosys/out/netlist_debug.v:64935:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264386:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__i_uart__obi_req_i ../yosys/out/netlist_debug.v:280150:47: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264390:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:61867:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5749 ../yosys/out/netlist_debug.v:61886:8: Example path: ASSIGNW %Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:58951:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2112' 58951 | wire \$abc$199608$new_n2112 ; | ^~~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:58951:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2112 ../yosys/out/netlist_debug.v:68722:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:68722:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_demux[4].i_demux.i_counter.down_i ../yosys/out/netlist_debug.v:60662:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60662:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n4425 ../yosys/out/netlist_debug.v:60674:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60674:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n4437 ../yosys/out/netlist_debug.v:61197:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61197:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5011 ../yosys/out/netlist_debug.v:58893:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58893:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$flatten___VhshPeKoP2Bz38adlE3Da8lp8voLXoUo47HrAJUzLYnH ../yosys/out/netlist_debug.v:61209:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61209:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5025 ../yosys/out/netlist_debug.v:62683:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62683:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n6690 ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__gen_dma.i_croc_idma__obi_write_rsp_i ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.obi_write_rsp_i ../yosys/out/netlist_debug.v:107984:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107984:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3077 ../yosys/out/netlist_debug.v:107985:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3078 ../technology/verilog/sg13g2_stdcell.v:1762:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107988:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3081 ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: ASSIGNW ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: __VdfgRegularize_he50b618e_0_1093 ../yosys/out/netlist_debug.v:152867:56: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106460:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__gen_dma.i_croc_idma__obi_write_req_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:58907:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2068 ../yosys/out/netlist_debug.v:58992:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58992:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2154 ../yosys/out/netlist_debug.v:59070:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59070:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2232 ../yosys/out/netlist_debug.v:59674:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59674:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2841 ../yosys/out/netlist_debug.v:59722:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59722:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2889 ../technology/verilog/sg13g2_stdcell.v:2127:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60566:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n3958 ../yosys/out/netlist_debug.v:64935:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264386:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__i_uart__obi_req_i ../yosys/out/netlist_debug.v:280150:47: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264390:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:61867:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5749 ../yosys/out/netlist_debug.v:61886:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61886:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5768 ../yosys/out/netlist_debug.v:61887:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61887:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5769 ../yosys/out/netlist_debug.v:62665:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62665:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n6671 ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW %Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:59045:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2207' 59045 | wire \$abc$199608$new_n2207 ; | ^~~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:59045:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2207 ../yosys/out/netlist_debug.v:59072:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59072:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2234 ../yosys/out/netlist_debug.v:59073:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59073:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2235 ../yosys/out/netlist_debug.v:59682:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59682:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2849 ../yosys/out/netlist_debug.v:59722:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59722:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2889 ../technology/verilog/sg13g2_stdcell.v:2127:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60566:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n3958 ../yosys/out/netlist_debug.v:64935:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264386:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__i_uart__obi_req_i ../yosys/out/netlist_debug.v:280150:47: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264390:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:61867:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5749 ../yosys/out/netlist_debug.v:61886:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61886:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5768 ../yosys/out/netlist_debug.v:61887:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61887:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5769 ../yosys/out/netlist_debug.v:62665:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62665:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n6671 ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__gen_dma.i_croc_idma__obi_write_rsp_i ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.obi_write_rsp_i ../yosys/out/netlist_debug.v:107984:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107984:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3077 ../yosys/out/netlist_debug.v:107985:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3078 ../technology/verilog/sg13g2_stdcell.v:1762:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107988:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3081 ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: ASSIGNW ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: __VdfgRegularize_he50b618e_0_1093 ../yosys/out/netlist_debug.v:152867:56: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106460:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__gen_dma.i_croc_idma__obi_write_req_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:58907:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2068 ../yosys/out/netlist_debug.v:58992:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58992:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2154 ../yosys/out/netlist_debug.v:59070:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59070:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2232 ../yosys/out/netlist_debug.v:59674:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59674:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2841 ../yosys/out/netlist_debug.v:59722:8: Example path: ASSIGNW %Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:60716:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n4481' 60716 | wire \$abc$199608$new_n4481 ; | ^~~~~~~~~~~~~~~~~~~~~~ ../yosys/out/netlist_debug.v:60716:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n4481 ../yosys/out/netlist_debug.v:60717:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60717:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n4482 ../yosys/out/netlist_debug.v:58877:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58877:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$flatten___Vhshfu0y2ieByA6zGXb6uvNHrB34SktJu9Rjg3XPXKig ../yosys/out/netlist_debug.v:60720:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60720:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n4486 ../yosys/out/netlist_debug.v:60739:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60739:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n4505 ../yosys/out/netlist_debug.v:62671:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62671:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n6677 ../yosys/out/netlist_debug.v:62683:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62683:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n6690 ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__gen_dma.i_croc_idma__obi_write_rsp_i ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106464:16: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.obi_write_rsp_i ../yosys/out/netlist_debug.v:107984:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107984:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3077 ../yosys/out/netlist_debug.v:107985:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107985:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3078 ../technology/verilog/sg13g2_stdcell.v:1762:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:107988:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.$abc$205972$new_n3081 ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: ASSIGNW ../technology/verilog/sg13g2_stdcell.v:208:22: Example path: __VdfgRegularize_he50b618e_0_1093 ../yosys/out/netlist_debug.v:152867:56: Example path: ASSIGNW ../yosys/out/netlist_debug.v:106460:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__gen_dma.i_croc_idma__obi_write_req_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:58907:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2068 ../yosys/out/netlist_debug.v:58992:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:58992:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2154 ../yosys/out/netlist_debug.v:59070:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59070:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2232 ../yosys/out/netlist_debug.v:59674:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59674:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2841 ../yosys/out/netlist_debug.v:59722:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:59722:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n2889 ../technology/verilog/sg13g2_stdcell.v:2127:6: Example path: ASSIGNW ../yosys/out/netlist_debug.v:60566:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n3958 ../yosys/out/netlist_debug.v:64935:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264386:16: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellinp__i_uart__obi_req_i ../yosys/out/netlist_debug.v:280150:47: Example path: ASSIGNW ../yosys/out/netlist_debug.v:264390:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o ../technology/verilog/sg13g2_udp.v:407:2: Example path: ALWAYS ../yosys/out/netlist_debug.v:61867:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5749 ../yosys/out/netlist_debug.v:61886:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61886:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5768 ../yosys/out/netlist_debug.v:61887:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:61887:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n5769 ../yosys/out/netlist_debug.v:62665:8: Example path: ASSIGNW ../yosys/out/netlist_debug.v:62665:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$199608$new_n6671 ../yosys/out/netlist_debug.v:106464:16: Example path: ASSIGNW make: Entering directory '/fosic/designs/croc/verilator/obj_dir_netlist_yosys' ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /foss/tools/verilator/share/verilator/include/verilated.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_dpi.o /foss/tools/verilator/share/verilator/include/verilated_dpi.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /foss/tools/verilator/share/verilator/include/verilated_timing.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /foss/tools/verilator/share/verilator/include/verilated_threads.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_croc_soc__pch.h -o Vtb_croc_soc__pch.h.fast.gch ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_croc_soc__pch.h -o Vtb_croc_soc__pch.h.slow.gch echo "" > Vtb_croc_soc__ALL.verilator_deplist.tmp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__ConstPool_0.o Vtb_croc_soc__ConstPool_0.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__Slow.o Vtb_croc_soc___024root__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__0__Slow.o Vtb_croc_soc___024root__0__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__1__Slow.o Vtb_croc_soc___024root__1__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__2__Slow.o Vtb_croc_soc___024root__2__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__3__Slow.o Vtb_croc_soc___024root__3__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__4__Slow.o Vtb_croc_soc___024root__4__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__5__Slow.o Vtb_croc_soc___024root__5__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__6__Slow.o Vtb_croc_soc___024root__6__Slow.cpp ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__Syms.o Vtb_croc_soc__Syms.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc_vm_classes_0.o Vtb_croc_soc_vm_classes_0.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc_vm_classes_1.o Vtb_croc_soc_vm_classes_1.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc_vm_classes_2.o Vtb_croc_soc_vm_classes_2.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc_vm_classes_3.o Vtb_croc_soc_vm_classes_3.cpp ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__Dpi.o Vtb_croc_soc__Dpi.cpp g++ -fuse-ld=mold verilated.o verilated_dpi.o verilated_timing.o verilated_threads.o Vtb_croc_soc__ALL.a -pthread -lpthread -latomic -o Vtb_croc_soc rm Vtb_croc_soc__ALL.verilator_deplist.tmp make: Leaving directory '/fosic/designs/croc/verilator/obj_dir_netlist_yosys' - V e r i l a t i o n R e p o r t: Verilator 5.042 2025-11-02 rev v5.042 - Verilator: Built from 240.270 MB sources in 402 modules, into 43.932 MB in 36 C++ files needing 0.034 MB - Verilator: Walltime 275.726 s (elab=0.949, cvt=16.773, bld=256.226); cpu 20.102 s on 4 threads; alloced 991.523 MB Found 8 test(s) to run ========================================= Running test_clint ... PASS Running test_compute ... PASS Running test_gpio ... PASS Running test_idma ... PASS Running test_interrupts ... PASS Running test_obi_timer ... PASS Running test_soc_ctrl ... PASS Running test_uart ... PASS ========================================= Summary: 8 passed, 0 failed, 8 total All tests passed. ============================================= Simulation completed ============================================= === Default: helloworld === Running program: ../sw/bin/helloworld.hex -Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace ClkFrequency: 20MHz UartRealBaudRate: 113636 @ 42100ns | [JTAG] Initialization success @ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000 @ 94650ns | [JTAG] Read 0x12345678 from 0x10000000 @ 94650ns | [JTAG] Read back correct data @ 94650ns | [JTAG] Loading binary from ../sw/bin/helloworld.hex @ 96950ns | [JTAG] Writing to memory @10000000 @ 106150ns | [JTAG] Writing to memory @1000000c @ 119950ns | [JTAG] Writing to memory @10000020 @ 1401050ns | [CORE] Waking core via CLINT msip @ 1401050ns | [JTAG] Writing 0x00000001 to 0x02040000 @ 1424100ns | [JTAG] Halting hart 0... @ 1437450ns | [JTAG] Halted @ 1439750ns | [JTAG] Resumed hart 0 @ 1439750ns | [CORE] Wait for end of code... @ 3663850ns | [UART] Hello World from Croc! @ 3663850ns | [UART] raw: '{'h48, 'h65, 'h6c, 'h6c, 'h6f, 'h20, 'h57, 'h6f, 'h72, 'h6c, 'h64, 'h20, 'h66, 'h72, 'h6f, 'h6d, 'h20, 'h43, 'h72, 'h6f, 'h63, 'h21, 'ha} @ 3688800ns | [JTAG] Simulation finished: SUCCESS - ../rtl/test/croc_vip.sv:278: Verilog $finish - S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02 - Verilator: $finish at 4ms; walltime 3.344 s; speed 1.103 ms/s - Verilator: cpu 3.344 s on 1 threads; alloced 57 MB === Default: print_config === Running program: ../sw/bin/test/print_config.hex -Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace ClkFrequency: 20MHz UartRealBaudRate: 113636 @ 42100ns | [JTAG] Initialization success @ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000 @ 94650ns | [JTAG] Read 0x12345678 from 0x10000000 @ 94650ns | [JTAG] Read back correct data @ 94650ns | [JTAG] Loading binary from ../sw/bin/test/print_config.hex @ 96950ns | [JTAG] Writing to memory @10000000 @ 106150ns | [JTAG] Writing to memory @1000000c @ 119950ns | [JTAG] Writing to memory @10000020 @ 1923150ns | [JTAG] Writing to memory @10000c5c @ 1930050ns | [CORE] Waking core via CLINT msip @ 1930050ns | [JTAG] Writing 0x00000001 to 0x02040000 @ 1953100ns | [JTAG] Halting hart 0... @ 1966450ns | [JTAG] Halted @ 1968750ns | [JTAG] Resumed hart 0 @ 1968750ns | [CORE] Wait for end of code... @ 4484450ns | [UART] Hello World from Croc v2! @ 4484450ns | [UART] raw: '{'h48, 'h65, 'h6c, 'h6c, 'h6f, 'h20, 'h57, 'h6f, 'h72, 'h6c, 'h64, 'h20, 'h66, 'h72, 'h6f, 'h6d, 'h20, 'h43, 'h72, 'h6f, 'h63, 'h20, 'h76, 'h32, 'h21, 'ha} @ 6033250ns | [UART] iDMAEnable: 0 @ 6033250ns | [UART] raw: '{'h20, 'h20, 'h69, 'h44, 'h4d, 'h41, 'h45, 'h6e, 'h61, 'h62, 'h6c, 'h65, 'h3a, 'h20, 'h30, 'ha} @ 8162850ns | [UART] Core: CVE2, RV32CIU @ 8162850ns | [UART] raw: '{'h20, 'h20, 'h43, 'h6f, 'h72, 'h65, 'h3a, 'h20, 'h43, 'h56, 'h45, 'h32, 'h2c, 'h20, 'h52, 'h56, 'h33, 'h32, 'h43, 'h49, 'h55, 'ha} @ 9614850ns | [UART] PMPEnable: 0 @ 9614850ns | [UART] raw: '{'h20, 'h20, 'h50, 'h4d, 'h50, 'h45, 'h6e, 'h61, 'h62, 'h6c, 'h65, 'h3a, 'h20, 'h30, 'ha} @ 12518850ns | [UART] SRAM: 2h banks x 200h words @ 12518850ns | [UART] raw: '{'h20, 'h20, 'h53, 'h52, 'h41, 'h4d, 'h3a, 'h20, 'h32, 'h68, 'h20, 'h62, 'h61, 'h6e, 'h6b, 'h73, 'h20, 'h78, 'h20, 'h32, 'h30, 'h30, 'h68, 'h20, 'h77, 'h6f, 'h72, 'h64, 'h73, 'ha} @ 13777250ns | [UART] Peripherals: @ 13777250ns | [UART] raw: '{'h50, 'h65, 'h72, 'h69, 'h70, 'h68, 'h65, 'h72, 'h61, 'h6c, 'h73, 'h3a, 'ha} @ 15713250ns | [UART] Debug : present @ 15713250ns | [UART] raw: '{'h20, 'h20, 'h44, 'h65, 'h62, 'h75, 'h67, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 17649250ns | [UART] Bootrom : present @ 17649250ns | [UART] raw: '{'h20, 'h20, 'h42, 'h6f, 'h6f, 'h74, 'h72, 'h6f, 'h6d, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 19585250ns | [UART] CLINT : present @ 19585250ns | [UART] raw: '{'h20, 'h20, 'h43, 'h4c, 'h49, 'h4e, 'h54, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 21521250ns | [UART] SoC Ctrl: present @ 21521250ns | [UART] raw: '{'h20, 'h20, 'h53, 'h6f, 'h43, 'h20, 'h43, 'h74, 'h72, 'h6c, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 23457250ns | [UART] UART : present @ 23457250ns | [UART] raw: '{'h20, 'h20, 'h55, 'h41, 'h52, 'h54, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 25393250ns | [UART] GPIO : present @ 25393250ns | [UART] raw: '{'h20, 'h20, 'h47, 'h50, 'h49, 'h4f, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 27329250ns | [UART] Timer : present @ 27329250ns | [UART] raw: '{'h20, 'h20, 'h54, 'h69, 'h6d, 'h65, 'h72, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 29652450ns | [UART] iDMA : not present @ 29652450ns | [UART] raw: '{'h20, 'h20, 'h69, 'h44, 'h4d, 'h41, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h6e, 'h6f, 'h74, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 31975650ns | [UART] User ROM: not present @ 31975650ns | [UART] raw: '{'h20, 'h20, 'h55, 'h73, 'h65, 'h72, 'h20, 'h52, 'h4f, 'h4d, 'h3a, 'h20, 'h6e, 'h6f, 'h74, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha} @ 32006650ns | [JTAG] Simulation finished: SUCCESS - ../rtl/test/croc_vip.sv:278: Verilog $finish - S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02 - Verilator: $finish at 32ms; walltime 30.186 s; speed 1.060 ms/s - Verilator: cpu 30.182 s on 1 threads; alloced 57 MB === iDMA: test_clint === Running program: ../sw/bin/test/test_clint.hex -Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace ClkFrequency: 20MHz UartRealBaudRate: 113636 @ 42100ns | [JTAG] Initialization success @ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000 @ 94650ns | [JTAG] Read 0x12345678 from 0x10000000 @ 94650ns | [JTAG] Read back correct data @ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_clint.hex @ 96950ns | [JTAG] Writing to memory @10000000 @ 106150ns | [JTAG] Writing to memory @1000000c @ 119950ns | [JTAG] Writing to memory @10000020 @ 1506850ns | [CORE] Waking core via CLINT msip @ 1506850ns | [JTAG] Writing 0x00000001 to 0x02040000 @ 1529900ns | [JTAG] Halting hart 0... @ 1543250ns | [JTAG] Halted @ 1545550ns | [JTAG] Resumed hart 0 @ 1545550ns | [CORE] Wait for end of code... @ 1646750ns | [JTAG] Simulation finished: SUCCESS - ../rtl/test/croc_vip.sv:278: Verilog $finish - S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02 - Verilator: $finish at 2ms; walltime 1.947 s; speed 845.829 us/s - Verilator: cpu 1.947 s on 1 threads; alloced 57 MB === iDMA: test_compute === Running program: ../sw/bin/test/test_compute.hex -Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace ClkFrequency: 20MHz UartRealBaudRate: 113636 @ 42100ns | [JTAG] Initialization success @ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000 @ 94650ns | [JTAG] Read 0x12345678 from 0x10000000 @ 94650ns | [JTAG] Read back correct data @ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_compute.hex @ 96950ns | [JTAG] Writing to memory @10000000 @ 106150ns | [JTAG] Writing to memory @1000000c @ 119950ns | [JTAG] Writing to memory @10000020 @ 1536750ns | [CORE] Waking core via CLINT msip @ 1536750ns | [JTAG] Writing 0x00000001 to 0x02040000 @ 1559800ns | [JTAG] Halting hart 0... @ 1573150ns | [JTAG] Halted @ 1575450ns | [JTAG] Resumed hart 0 @ 1575450ns | [CORE] Wait for end of code... @ 1610050ns | [JTAG] Simulation finished: SUCCESS - ../rtl/test/croc_vip.sv:278: Verilog $finish - S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02 - Verilator: $finish at 2ms; walltime 1.896 s; speed 849.403 us/s - Verilator: cpu 1.896 s on 1 threads; alloced 57 MB === iDMA: test_gpio === Running program: ../sw/bin/test/test_gpio.hex -Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace ClkFrequency: 20MHz UartRealBaudRate: 113636 @ 42100ns | [JTAG] Initialization success @ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000 @ 94650ns | [JTAG] Read 0x12345678 from 0x10000000 @ 94650ns | [JTAG] Read back correct data @ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_gpio.hex @ 96950ns | [JTAG] Writing to memory @10000000 @ 106150ns | [JTAG] Writing to memory @1000000c @ 119950ns | [JTAG] Writing to memory @10000020 @ 1541350ns | [CORE] Waking core via CLINT msip @ 1541350ns | [JTAG] Writing 0x00000001 to 0x02040000 @ 1564400ns | [JTAG] Halting hart 0... @ 1577750ns | [JTAG] Halted @ 1580050ns | [JTAG] Resumed hart 0 @ 1580050ns | [CORE] Wait for end of code... @ 1614650ns | [JTAG] Simulation finished: SUCCESS - ../rtl/test/croc_vip.sv:278: Verilog $finish - S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02 - Verilator: $finish at 2ms; walltime 1.894 s; speed 852.595 us/s - Verilator: cpu 1.894 s on 1 threads; alloced 57 MB === iDMA: test_idma === Running program: ../sw/bin/test/test_idma.hex -Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace ClkFrequency: 20MHz UartRealBaudRate: 113636 @ 42100ns | [JTAG] Initialization success @ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000 @ 94650ns | [JTAG] Read 0x12345678 from 0x10000000 @ 94650ns | [JTAG] Read back correct data @ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_idma.hex @ 96950ns | [JTAG] Writing to memory @10000000 @ 106150ns | [JTAG] Writing to memory @1000000c @ 119950ns | [JTAG] Writing to memory @10000020 @ 1617250ns | [JTAG] Writing to memory @10000a48 @ 1658650ns | [CORE] Waking core via CLINT msip @ 1658650ns | [JTAG] Writing 0x00000001 to 0x02040000 @ 1681700ns | [JTAG] Halting hart 0... @ 1695050ns | [JTAG] Halted @ 1697350ns | [JTAG] Resumed hart 0 @ 1697350ns | [CORE] Wait for end of code... @ 1731950ns | [JTAG] Simulation finished: SUCCESS - ../rtl/test/croc_vip.sv:278: Verilog $finish - S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02 - Verilator: $finish at 2ms; walltime 2.110 s; speed 821.161 us/s - Verilator: cpu 2.109 s on 1 threads; alloced 57 MB === iDMA: test_interrupts === Running program: ../sw/bin/test/test_interrupts.hex -Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace ClkFrequency: 20MHz UartRealBaudRate: 113636 @ 42100ns | [JTAG] Initialization success @ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000 @ 94650ns | [JTAG] Read 0x12345678 from 0x10000000 @ 94650ns | [JTAG] Read back correct data @ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_interrupts.hex @ 96950ns | [JTAG] Writing to memory @10000000 @ 106150ns | [JTAG] Writing to memory @1000000c @ 119950ns | [JTAG] Writing to memory @10000020 @ 1516050ns | [JTAG] Writing to memory @10000998 @ 1525250ns | [CORE] Waking core via CLINT msip @ 1525250ns | [JTAG] Writing 0x00000001 to 0x02040000 @ 1548300ns | [JTAG] Halting hart 0... @ 1561650ns | [JTAG] Halted @ 1563950ns | [JTAG] Resumed hart 0 @ 1563950ns | [CORE] Wait for end of code... @ 1631850ns | [JTAG] Simulation finished: SUCCESS - ../rtl/test/croc_vip.sv:278: Verilog $finish - S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02 - Verilator: $finish at 2ms; walltime 1.920 s; speed 849.927 us/s - Verilator: cpu 1.920 s on 1 threads; alloced 57 MB === iDMA: test_obi_timer === Running program: ../sw/bin/test/test_obi_timer.hex -Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace ClkFrequency: 20MHz UartRealBaudRate: 113636 @ 42100ns | [JTAG] Initialization success @ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000 @ 94650ns | [JTAG] Read 0x12345678 from 0x10000000 @ 94650ns | [JTAG] Read back correct data @ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_obi_timer.hex @ 96950ns | [JTAG] Writing to memory @10000000 @ 106150ns | [JTAG] Writing to memory @1000000c @ 119950ns | [JTAG] Writing to memory @10000020 @ 1513750ns | [CORE] Waking core via CLINT msip @ 1513750ns | [JTAG] Writing 0x00000001 to 0x02040000 @ 1536800ns | [JTAG] Halting hart 0... @ 1550150ns | [JTAG] Halted @ 1552450ns | [JTAG] Resumed hart 0 @ 1552450ns | [CORE] Wait for end of code... @ 1620350ns | [JTAG] Simulation finished: SUCCESS - ../rtl/test/croc_vip.sv:278: Verilog $finish - S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02 - Verilator: $finish at 2ms; walltime 1.929 s; speed 840.181 us/s - Verilator: cpu 1.929 s on 1 threads; alloced 57 MB === iDMA: test_soc_ctrl === Running program: ../sw/bin/test/test_soc_ctrl.hex -Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace ClkFrequency: 20MHz UartRealBaudRate: 113636 @ 42100ns | [JTAG] Initialization success @ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000 @ 94650ns | [JTAG] Read 0x12345678 from 0x10000000 @ 94650ns | [JTAG] Read back correct data @ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_soc_ctrl.hex @ 96950ns | [JTAG] Writing to memory @10000000 @ 106150ns | [JTAG] Writing to memory @1000000c @ 119950ns | [JTAG] Writing to memory @10000020 @ 1465450ns | [CORE] Waking core via CLINT msip @ 1465450ns | [JTAG] Writing 0x00000001 to 0x02040000 @ 1488500ns | [JTAG] Halting hart 0... @ 1501850ns | [JTAG] Halted @ 1504150ns | [JTAG] Resumed hart 0 @ 1504150ns | [CORE] Wait for end of code... @ 1538750ns | [JTAG] Simulation finished: SUCCESS - ../rtl/test/croc_vip.sv:278: Verilog $finish - S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02 - Verilator: $finish at 2ms; walltime 1.803 s; speed 853.589 us/s - Verilator: cpu 1.803 s on 1 threads; alloced 57 MB === iDMA: test_uart === Running program: ../sw/bin/test/test_uart.hex -Info: ../rtl/test/tb_croc_soc.sv:168: $dumpvar ignored, as Verilated without --trace ClkFrequency: 20MHz UartRealBaudRate: 113636 @ 42100ns | [JTAG] Initialization success @ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000 @ 94650ns | [JTAG] Read 0x12345678 from 0x10000000 @ 94650ns | [JTAG] Read back correct data @ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_uart.hex @ 96950ns | [JTAG] Writing to memory @10000000 @ 106150ns | [JTAG] Writing to memory @1000000c @ 119950ns | [JTAG] Writing to memory @10000020 @ 1479250ns | [CORE] Waking core via CLINT msip @ 1479250ns | [JTAG] Writing 0x00000001 to 0x02040000 @ 1502300ns | [JTAG] Halting hart 0... @ 1515650ns | [JTAG] Halted @ 1517950ns | [JTAG] Resumed hart 0 @ 1517950ns | [CORE] Wait for end of code... @ 1818950ns | [JTAG] Simulation finished: SUCCESS - ../rtl/test/croc_vip.sv:278: Verilog $finish @ 1818975ns | [UART] TX - S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02 - Verilator: $finish at 2ms; walltime 2.188 s; speed 831.460 us/s - Verilator: cpu 2.188 s on 1 threads; alloced 57 MB