[INFO][ENV] Croc root: /fosic/designs/croc [INFO][ENV] PDK root: /fosic/designs/croc/technology [INFO][ENV] Croc PDK: sg13cmos5l [INFO][ENV] Active technology view: public mirror [INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout [INFO][ENV] Bender PDK args: -D IHP_SG13CMOS5L=1 [INFO][ENV] Tech LEF: sg13cmos5l_tech.lef [INFO][ENV] IO LEF/GDS: sg13cmos5l_io.lef/sg13cmos5l_io.gds [INFO][ENV] IO Liberty tt/ff: sg13cmos5l_io_typ_1p2V_3p3V_25C.lib/sg13cmos5l_io_fast_1p32V_3p6V_m40C.lib [INFO][ENV] Bondpad LEF/GDS: bondpad5l_70x70.lef/bondpad5l_70x70.gds [INFO][OpenROAD] Running scripts/04_routing.tcl [13:28 UTC] OpenROAD v2.0-27244-gfecb04286 [13:28 UTC] Features included (+) or not (-): +GPU +GUI +Python [13:28 UTC] This program is licensed under the BSD-3 license. See the LICENSE file for details. [13:28 UTC] Components of this program may be licensed under more restrictive licenses which must be honored. [13:28 UTC] Setting up project croc [13:28 UTC] - Netlist: ../yosys/out/croc_yosys.v [13:28 UTC] - Project: croc [13:28 UTC] - Top design: croc_chip [13:28 UTC] - Report directory: reports [13:28 UTC] - Save directory: save [13:28 UTC] - Output directory: out [13:28 UTC] Init standard cells [13:28 UTC] Init IO cells [13:28 UTC] Init SRAM macros [13:28 UTC] Init tech-lef [13:28 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/sg13cmos5l_tech.lef, created 15 layers, 52 vias [13:28 UTC] Init cell-lef [13:28 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/sg13g2_stdcell.lef, created 84 library cells [13:28 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/sg13cmos5l_io.lef, created 22 library cells [13:28 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/bondpad5l_70x70.lef, created 1 library cells [13:28 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_64x64_c2_bm_bist.lef, created 1 library cells [13:28 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_2048x64_c2_bm_bist.lef, created 1 library cells [13:28 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_1024x64_c2_bm_bist.lef, created 1 library cells [13:28 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_512x64_c2_bm_bist.lef, created 1 library cells [13:28 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_256x64_c2_bm_bist.lef, created 1 library cells [13:28 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_512x32_c2_bm_bist.lef, created 1 library cells [13:28 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_256x48_c2_bm_bist.lef, created 1 library cells [13:28 UTC] Loading checkpoint 03_croc.cts [13:28 UTC] Loading from ZIP file: save/03_croc.cts.zip [13:28 UTC] ############################################################################### [13:28 UTC] # Stage 04: ROUTING [13:28 UTC] ############################################################################### [13:28 UTC] ############################################################################### [13:28 UTC] # 04-01: Global Route [13:28 UTC] ############################################################################### [13:28 UTC] Global route [13:28 UTC] Estimate parasitics [13:28 UTC] Saving checkpoint 04-01_croc.grt [13:28 UTC] Time: 18.449194 sec deltaT: 18.397562 [13:28 UTC] saving image to reports/04-01_croc.grt.png [13:28 UTC] [WARNING GUI-0076] QStandardPaths: runtime directory '/tmp/runtime-default' is not owned by UID 1001, but a directory permissions 0777 owned by UID 0 GID 0 [13:28 UTC] [WARNING GUI-0076] QStandardPaths: runtime directory '/tmp/runtime-default' is not owned by UID 1001, but a directory permissions 0777 owned by UID 0 GID 0 [13:28 UTC] Perform buffer insertion... [13:28 UTC] Iteration | Area | Resized | Buffers | Nets repaired | Remaining [13:28 UTC] --------------------------------------------------------------------- [13:28 UTC] 0 | +0.0% | 0 | 0 | 0 | 33697 [13:28 UTC] 1000 | +0.0% | 0 | 0 | 0 | 32697 [13:28 UTC] 2000 | +0.0% | 0 | 0 | 0 | 31697 [13:28 UTC] 3000 | +0.0% | 0 | 0 | 0 | 30697 [13:28 UTC] 4000 | +0.0% | 0 | 0 | 0 | 29697 [13:28 UTC] 5000 | +0.0% | 0 | 0 | 0 | 28697 [13:28 UTC] 6000 | +0.0% | 0 | 0 | 0 | 27697 [13:28 UTC] 7000 | +0.0% | 0 | 0 | 0 | 26697 [13:28 UTC] 8000 | +0.0% | 0 | 0 | 0 | 25697 [13:28 UTC] 9000 | +0.0% | 0 | 0 | 0 | 24697 [13:28 UTC] 10000 | +0.0% | 0 | 0 | 0 | 23697 [13:28 UTC] 11000 | +0.0% | 0 | 0 | 0 | 22697 [13:28 UTC] 12000 | +0.0% | 0 | 0 | 0 | 21697 [13:28 UTC] 13000 | +0.0% | 0 | 0 | 0 | 20697 [13:28 UTC] 14000 | +0.0% | 0 | 1 | 1 | 19697 [13:28 UTC] 15000 | +0.0% | 0 | 1 | 1 | 18697 [13:28 UTC] 16000 | +0.0% | 0 | 1 | 1 | 17697 [13:28 UTC] 17000 | +0.0% | 0 | 1 | 1 | 16697 [13:28 UTC] 18000 | +0.0% | 0 | 1 | 1 | 15697 [13:28 UTC] 19000 | +0.0% | 0 | 1 | 1 | 14697 [13:28 UTC] 20000 | +0.0% | 0 | 1 | 1 | 13697 [13:28 UTC] 21000 | +0.0% | 0 | 1 | 1 | 12697 [13:28 UTC] 22000 | +0.0% | 0 | 1 | 1 | 11697 [13:28 UTC] 23000 | +0.0% | 0 | 2 | 2 | 10697 [13:28 UTC] 24000 | +0.0% | 0 | 2 | 2 | 9697 [13:28 UTC] 25000 | +0.0% | 0 | 2 | 2 | 8697 [13:28 UTC] 26000 | +0.0% | 0 | 2 | 2 | 7697 [13:28 UTC] 27000 | +0.0% | 0 | 2 | 2 | 6697 [13:28 UTC] 28000 | +0.0% | 0 | 2 | 2 | 5697 [13:28 UTC] 29000 | +0.0% | 0 | 2 | 2 | 4697 [13:28 UTC] 30000 | +0.0% | 0 | 2 | 2 | 3697 [13:28 UTC] 31000 | +0.0% | 0 | 2 | 2 | 2697 [13:28 UTC] 32000 | +0.0% | 0 | 2 | 2 | 1697 [13:28 UTC] 33000 | +0.1% | 0 | 66 | 66 | 697 [13:28 UTC] final | +0.1% | 0 | 66 | 66 | 0 [13:28 UTC] --------------------------------------------------------------------- [13:28 UTC] [INFO RSZ-0035] Found 2 fanout violations. [13:28 UTC] [INFO RSZ-0036] Found 64 capacitance violations. [13:28 UTC] [INFO RSZ-0038] Inserted 66 buffers in 66 nets. [13:28 UTC] Repair setup and hold violations... [13:28 UTC] [INFO RSZ-0100] Repair move sequence: UnbufferMove SizeUpMove SwapPinsMove BufferMove CloneMove SplitLoadMove [13:28 UTC] [INFO RSZ-0094] Found 393 endpoints with setup violations. [13:28 UTC] [INFO RSZ-0099] Repairing 393 out of 393 (100.00%) violating endpoints... [13:28 UTC] Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst [13:28 UTC] | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt [13:28 UTC] -------------------------------------------------------------------------------------------------------------- [13:28 UTC] 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.369 | -60.4 | 393 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 10 | 0 | 4 | 1 | 0 | 4 | +0.0% | -0.151 | -5.7 | 393 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 19 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 391 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 20 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 391 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 20 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 390 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 21 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 389 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 22 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 388 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 23 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 387 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 24 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 386 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 25 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 385 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 26 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 384 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 27 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 383 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 28 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 382 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 29 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 381 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 30 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 381 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 30 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 380 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 31 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 379 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 32 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 378 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 33 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 377 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 34 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 376 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 35 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 375 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 36 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 374 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 37 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 373 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 38 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 372 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 39 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 371 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 40 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 371 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 40 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 370 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 41 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 369 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 42 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 368 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 43 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 367 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 44 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 366 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 45 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 365 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 46 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 364 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 47 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 363 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 48 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 362 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 49 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 361 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 50 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 361 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 50 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 360 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 51 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 359 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 52 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 358 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 53 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 357 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 54 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 356 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 55 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 355 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 56 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 354 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 57 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 353 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 58 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 352 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 59 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 351 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 60 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 351 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 60 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 350 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 61 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 349 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 62 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 348 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 63 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 347 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 64 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 346 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 65 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 345 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 66 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 344 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 67 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 343 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 68 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 342 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 69 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 341 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 70 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 341 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 70 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 340 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 71 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 339 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 72 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 338 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 73 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 337 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 74 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 336 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 75 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 335 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 76 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 334 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 77 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 333 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 78 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 332 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 79 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 331 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 80 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 331 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 80 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 330 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 81 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 329 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 82 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 328 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 83 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 327 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 84 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 326 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 85 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 325 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D 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0 | 8 | +0.0% | -0.000 | -0.0 | 66 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 345 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 65 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 346 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 64 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 347 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 63 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 348 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 62 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 349 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 61 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 350 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 61 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 350 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 60 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 351 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 59 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 352 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 58 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 353 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 57 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 354 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 56 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 355 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 55 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 356 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 54 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 357 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 53 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 358 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 52 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 359 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 51 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 360 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 51 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 360 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 50 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 361 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 49 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 362 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 48 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 363 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 47 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 364 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 46 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 365 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 45 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 366 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 44 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 367 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 43 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 368 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 42 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 369 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 41 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 370 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 41 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 370 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 40 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 371 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 39 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 372 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 38 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 373 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 37 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 374 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 36 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 375 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 35 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 376 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 34 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 377 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 33 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 378 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 32 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 379 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 31 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 380 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 31 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 380 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 30 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 381 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 29 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 382 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 28 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 383 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 27 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 384 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 26 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 385 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 25 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 386 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 24 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 387 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 23 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 388 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 22 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 389 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 21 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 390 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 21 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 390 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 20 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 391 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 19 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 392 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 18 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 393 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 17 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 394 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 16 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 395 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 15 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 396 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 14 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 397 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 13 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 398 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 12 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 399 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 11 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 400 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 11 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 400 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 10 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 401 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 9 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 402 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 8 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 403 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 7 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 404 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 6 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 405 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 5 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 406 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 4 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 407 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 3 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 408 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 2 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 409 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 1 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 410 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 1 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 410 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 0 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 411 | 0 | 8 | 3 | 0 | 8 | +0.0% | -0.000 | -0.0 | 0 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] 413* | 0 | 9 | 3 | 0 | 8 | +0.0% | 0.033 | 0.0 | 0 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] final | 0 | 9 | 3 | 0 | 8 | +0.0% | 0.033 | 0.0 | 0 | i_croc_soc/i_croc/i_core_wrap/i_core.crash_dump_o_42__reg/D [13:28 UTC] -------------------------------------------------------------------------------------------------------------- [13:28 UTC] [INFO RSZ-0040] Inserted 3 buffers. [13:28 UTC] [INFO RSZ-0051] Resized 9 instances: 9 up, 0 up match, 0 down, 0 VT [13:28 UTC] [INFO RSZ-0043] Swapped pins on 8 instances. [13:28 UTC] [INFO RSZ-0046] Found 593 endpoints with hold violations. [13:28 UTC] Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint [13:28 UTC] -------------------------------------------------------------------------------------- [13:28 UTC] 0 | 0 | 0 | 0 | +0.0% | -0.034 | -0.034 | i_croc_soc/i_croc/i_dmi_jtag/i_dmi_cdc.i_cdc_req/i_cdc_reset_ctrlr/i_cdc_reset_ctrlr_half_b/i_state_transition_cdc_src/i_sync/serial_o_reg/D [13:28 UTC] 10 | 0 | 9 | 0 | +0.0% | 0.031 | 0.000 | i_croc_soc/i_croc/i_gpio/gen_gpios[8].i_sync/serial_o_reg/D [13:28 UTC] 20 | 0 | 19 | 0 | +0.0% | 0.032 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_modem.i_sync_cd/serial_o_reg/D [13:28 UTC] 30 | 0 | 29 | 0 | +0.1% | 0.033 | 0.000 | i_croc_soc/i_croc/i_gpio/gen_gpios[25].serial_q_reg/D [13:28 UTC] 40 | 0 | 39 | 0 | +0.1% | 0.034 | 0.000 | i_croc_soc/i_croc/i_gpio/gen_gpios[16].i_sync/serial_o_reg/D [13:28 UTC] 50 | 0 | 49 | 0 | +0.1% | 0.048 | 0.000 | i_croc_soc/i_croc/i_dmi_jtag/i_dmi_cdc.i_cdc_resp/i_dst/req_synced_q1_reg/D [13:28 UTC] 60 | 0 | 59 | 0 | +0.1% | 0.053 | 0.000 | i_croc_soc/i_croc/i_gpio/gen_gpios[5].serial_q_reg/D [13:28 UTC] 70 | 0 | 69 | 0 | +0.2% | 0.060 | 0.000 | i_croc_soc/i_croc/i_gpio/gen_gpios[23].i_sync/serial_o_reg/D [13:28 UTC] 80 | 0 | 79 | 0 | +0.2% | 0.079 | 0.000 | i_croc_soc/i_croc/i_dmi_jtag/i_dmi_jtag_tap.idcode_q_23__reg/D [13:28 UTC] 90 | 0 | 89 | 0 | +0.2% | 0.084 | 0.000 | i_croc_soc/i_croc/i_gpio/i_reg_file.reg_q_177__reg/D [13:28 UTC] 100 | 0 | 99 | 0 | +0.2% | 0.086 | 0.000 | i_croc_soc/i_croc/i_core_wrap/i_core.cs_registers_i/dcsr_q_30__reg/D [13:28 UTC] 110 | 0 | 109 | 0 | +0.3% | 0.087 | 0.000 | i_croc_soc/i_croc/i_core_wrap/i_core.cs_registers_i/dcsr_q_28__reg/D [13:28 UTC] 120 | 0 | 119 | 0 | +0.3% | 0.088 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/i_dm_csrs.i_fifo.mem_q_14__reg/D [13:28 UTC] 130 | 0 | 129 | 0 | +0.3% | 0.089 | 0.000 | i_croc_soc/i_croc/i_core_wrap/i_core.cs_registers_i/dscratch0_q_22__reg/D [13:28 UTC] 140 | 0 | 139 | 0 | +0.3% | 0.090 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_rx.i_fifo_v3.mem_q_99__reg/D [13:28 UTC] 150 | 0 | 150 | 0 | +0.4% | 0.091 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_rx.i_fifo_v3.mem_q_119__reg/D [13:28 UTC] 160 | 0 | 160 | 0 | +0.4% | 0.091 | 0.000 | i_croc_soc/i_croc/i_core_wrap/i_core.cs_registers_i/dscratch0_q_19__reg/D [13:28 UTC] 170 | 0 | 170 | 0 | +0.4% | 0.091 | 0.000 | i_croc_soc/i_croc/i_soc_ctrl/core_status_q_29__reg/D [13:28 UTC] 180 | 0 | 180 | 0 | +0.4% | 0.092 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_rx.i_fifo_v3.mem_q_31__reg/D [13:28 UTC] 190 | 0 | 190 | 0 | +0.5% | 0.092 | 0.000 | i_croc_soc/i_croc/i_soc_ctrl/core_status_q_22__reg/D [13:28 UTC] 200 | 0 | 200 | 0 | +0.5% | 0.092 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_interrupts.intrpt_reg_q_0__reg/D [13:28 UTC] 210 | 0 | 210 | 0 | +0.5% | 0.092 | 0.000 | i_croc_soc/i_croc/i_soc_ctrl/core_status_q_17__reg/D [13:28 UTC] 220 | 0 | 220 | 0 | +0.5% | 0.092 | 0.000 | i_croc_soc/i_croc/i_gpio/i_reg_file.reg_q_191__reg/D [13:28 UTC] 230 | 0 | 230 | 0 | +0.5% | 0.092 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_rx.i_fifo_v3.mem_q_4__reg/D [13:28 UTC] 240 | 0 | 240 | 0 | +0.6% | 0.093 | 0.000 | i_croc_soc/i_croc/i_core_wrap/i_core.cs_registers_i/dscratch0_q_10__reg/D [13:28 UTC] 250 | 0 | 250 | 0 | +0.6% | 0.093 | 0.000 | i_croc_soc/i_croc/i_soc_ctrl/boot_addr_q_14__reg/D [13:28 UTC] 260 | 0 | 260 | 0 | +0.6% | 0.093 | 0.000 | i_croc_soc/i_croc/i_core_wrap/i_core.cs_registers_i/dscratch1_q_23__reg/D [13:28 UTC] 270 | 0 | 270 | 0 | +0.6% | 0.093 | 0.000 | i_croc_soc/i_croc/i_gpio/i_reg_file.reg_q_160__reg/D [13:28 UTC] 280 | 0 | 280 | 0 | +0.7% | 0.093 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_tx.i_fifo_v3.mem_q_97__reg/D [13:28 UTC] 290 | 0 | 290 | 0 | +0.7% | 0.093 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_tx.i_fifo_v3.mem_q_26__reg/D [13:28 UTC] 300 | 0 | 300 | 0 | +0.7% | 0.094 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_rx.i_fifo_v3.mem_q_38__reg/D [13:28 UTC] 310 | 0 | 310 | 0 | +0.7% | 0.094 | 0.000 | i_croc_soc/i_croc/i_soc_ctrl/boot_addr_q_17__reg/D [13:28 UTC] 320 | 0 | 320 | 0 | +0.8% | 0.094 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/cmd_31__reg/D [13:28 UTC] 330 | 0 | 330 | 0 | +0.8% | 0.094 | 0.000 | i_croc_soc/i_croc/i_core_wrap/i_core.cs_registers_i/mscratch_q_22__reg/D [13:28 UTC] 340 | 0 | 340 | 0 | +0.8% | 0.094 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_tx.i_fifo_v3.mem_q_98__reg/D [13:28 UTC] 350 | 0 | 350 | 0 | +0.8% | 0.094 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_tx.i_fifo_v3.mem_q_10__reg/D [13:28 UTC] 360 | 0 | 361 | 0 | +0.9% | 0.095 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_tx.i_fifo_v3.mem_q_96__reg/D [13:28 UTC] 370 | 0 | 371 | 0 | +0.9% | 0.095 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/i_dm_csrs.sbdata_q_39__reg/D [13:28 UTC] 380 | 0 | 381 | 0 | +0.9% | 0.095 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/i_dm_csrs.i_fifo.mem_q_3__reg/D [13:28 UTC] 390 | 0 | 391 | 0 | +0.9% | 0.095 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_tx.i_fifo_v3.mem_q_17__reg/D [13:28 UTC] 400 | 0 | 401 | 0 | +1.0% | 0.095 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/i_dm_csrs.sbdata_q_34__reg/D [13:28 UTC] 410 | 0 | 411 | 0 | +1.0% | 0.095 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/i_dm_csrs.sbdata_q_57__reg/D [13:28 UTC] 420 | 0 | 421 | 0 | +1.0% | 0.096 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_rx.i_fifo_v3.mem_q_32__reg/D [13:28 UTC] 430 | 0 | 431 | 0 | +1.0% | 0.096 | 0.000 | i_croc_soc/i_croc/i_soc_ctrl/boot_addr_q_19__reg/D [13:28 UTC] 440 | 0 | 441 | 0 | +1.0% | 0.096 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_rx.i_fifo_v3.mem_q_66__reg/D [13:28 UTC] 450 | 0 | 451 | 0 | +1.1% | 0.096 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_tx.i_fifo_v3.mem_q_122__reg/D [13:28 UTC] 460 | 0 | 461 | 0 | +1.1% | 0.096 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/i_dm_csrs.sbdata_q_45__reg/D [13:28 UTC] 470 | 0 | 471 | 0 | +1.1% | 0.097 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_rx.i_fifo_v3.mem_q_1__reg/D [13:28 UTC] 480 | 0 | 481 | 0 | +1.1% | 0.097 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/i_dm_csrs.i_fifo.mem_q_11__reg/D [13:28 UTC] 490 | 0 | 491 | 0 | +1.2% | 0.097 | 0.000 | i_croc_soc/i_croc/i_dmi_jtag/dtmcs_q_6__reg/D [13:28 UTC] 500 | 0 | 501 | 0 | +1.2% | 0.097 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/i_dm_csrs.i_fifo.mem_q_17__reg/D [13:28 UTC] 510 | 0 | 511 | 0 | +1.2% | 0.098 | 0.000 | i_croc_soc/i_croc/i_core_wrap/i_core.cs_registers_i/mcycle_counter_i.counter_val_o_15__reg/D [13:28 UTC] 520 | 0 | 521 | 0 | +1.2% | 0.098 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_rx.i_fifo_v3.mem_q_126__reg/D [13:28 UTC] 530 | 0 | 531 | 0 | +1.3% | 0.098 | 0.000 | i_croc_soc/i_croc/i_uart/i_uart_rx.i_fifo_v3.mem_q_56__reg/D [13:28 UTC] 540 | 0 | 541 | 0 | +1.3% | 0.099 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/i_dm_csrs.progbuf_o_4__reg/D [13:28 UTC] 550 | 0 | 551 | 0 | +1.3% | 0.099 | 0.000 | i_croc_soc/i_croc/i_core_wrap/i_core.cs_registers_i/mscratch_q_10__reg/D [13:28 UTC] 560 | 0 | 561 | 0 | +1.3% | 0.099 | 0.000 | i_croc_soc/i_croc/i_dmi_jtag/dtmcs_q_23__reg/D [13:28 UTC] 570 | 0 | 571 | 0 | +1.4% | 0.099 | 0.000 | i_croc_soc/i_croc/i_dmi_jtag/dtmcs_q_4__reg/D [13:28 UTC] 580 | 0 | 581 | 0 | +1.4% | 0.099 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/i_dm_mem.rdata_q_47__reg/D [13:28 UTC] 590 | 0 | 591 | 0 | +1.4% | 0.100 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/i_dm_csrs.sbdata_q_43__reg/D [13:28 UTC] final | 0 | 595 | 0 | +1.4% | 0.100 | 0.000 | i_croc_soc/i_croc/i_dm_top.i_dm_top/i_dm_csrs.progbuf_o_171__reg/D [13:28 UTC] -------------------------------------------------------------------------------------- [13:28 UTC] [INFO RSZ-0032] Inserted 595 hold buffers. [13:28 UTC] GRT incremental... [13:28 UTC] Placement Analysis [13:28 UTC] --------------------------------- [13:28 UTC] total displacement 4046.5 u [13:28 UTC] average displacement 0.1 u [13:28 UTC] max displacement 11.3 u [13:28 UTC] original HPWL 1520392.3 u [13:28 UTC] legalized HPWL 1523326.9 u [13:28 UTC] delta HPWL 0 % [13:28 UTC] [13:28 UTC] [INFO GRT-0009] rerouting 1180 nets. [13:28 UTC] [INFO GRT-0001] Minimum degree: 2 [13:28 UTC] [INFO GRT-0002] Maximum degree: 26 [13:28 UTC] [13:28 UTC] [INFO GRT-0096] Final congestion report: [13:28 UTC] Layer Resource Demand Usage (%) Max H / Max V / Total Overflow [13:28 UTC] --------------------------------------------------------------------------------------- [13:28 UTC] Metal1 0 0 0.00% 0 / 0 / 0 [13:28 UTC] Metal2 867547 117766 13.57% 0 / 0 / 0 [13:28 UTC] Metal3 706179 114470 16.21% 0 / 0 / 0 [13:28 UTC] Metal4 571202 1938 0.34% 0 / 0 / 0 [13:28 UTC] TopMetal1 49936 181 0.36% 0 / 0 / 0 [13:28 UTC] --------------------------------------------------------------------------------------- [13:28 UTC] Total 2194864 234355 10.68% 0 / 0 / 0 [13:28 UTC] [13:28 UTC] [INFO GRT-0018] Total wirelength: 2366618 um [13:28 UTC] [INFO GRT-0014] Routed nets: 33647 [13:28 UTC] Saving checkpoint 04-01_croc.grt_repaired [13:28 UTC] Time: 56.622041 sec deltaT: 38.172830000000005 [13:28 UTC] saving image to reports/04-01_croc.grt_repaired.png [13:28 UTC] [WARNING GUI-0076] QStandardPaths: runtime directory '/tmp/runtime-default' is not owned by UID 1001, but a directory permissions 0777 owned by UID 0 GID 0 [13:28 UTC] [WARNING GUI-0076] QStandardPaths: runtime directory '/tmp/runtime-default' is not owned by UID 1001, but a directory permissions 0777 owned by UID 0 GID 0 [13:28 UTC] [WARNING GUI-0076] QStandardPaths: runtime directory '/tmp/runtime-default' is not owned by UID 1001, but a directory permissions 0777 owned by UID 0 GID 0 [13:28 UTC] ############################################################################### [13:28 UTC] # 04-02: Detailed Route [13:28 UTC] ############################################################################### [13:28 UTC] [INFO GRT-0006] Repairing antennas, iteration 1. [13:29 UTC] [INFO GRT-0012] Found 75 antenna violations. [13:29 UTC] [INFO GRT-0302] Inserted 91 jumpers for 74 nets. [13:29 UTC] [INFO GRT-0012] Found 21 antenna violations. [13:29 UTC] [INFO GRT-0015] Inserted 24 diodes. [13:29 UTC] [INFO GRT-0009] rerouting 29 nets. [13:29 UTC] [INFO GRT-0001] Minimum degree: 2 [13:29 UTC] [INFO GRT-0002] Maximum degree: 9 [13:29 UTC] [INFO GRT-0006] Repairing antennas, iteration 2. [13:29 UTC] [INFO GRT-0012] Found 0 antenna violations. [13:29 UTC] Detailed route [13:29 UTC] [INFO ORD-0030] Using 4 thread(s). [13:29 UTC] [INFO DRT-0149] Reading tech and libs. [13:29 UTC] [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer Cont [13:29 UTC] [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer Via1 [13:29 UTC] [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer Via1 [13:29 UTC] [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer Via2 [13:29 UTC] [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer Via3 [13:29 UTC] [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer TopVia1 [13:29 UTC] [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer TopVia1 [13:29 UTC] [13:29 UTC] Units: 1000 [13:29 UTC] Number of layers: 11 [13:29 UTC] Number of macros: 114 [13:29 UTC] Number of vias: 64 [13:29 UTC] Number of viarulegen: 4 [13:29 UTC] [13:29 UTC] [INFO DRT-0150] Reading design. [13:29 UTC] [13:29 UTC] Design: croc_chip [13:29 UTC] Die area: ( 0 0 ) ( 1916000 1916000 ) [13:29 UTC] Number of track patterns: 10 [13:29 UTC] Number of DEF vias: 0 [13:29 UTC] Number of components: 34518 [13:29 UTC] Number of terminals: 52 [13:29 UTC] Number of snets: 52 [13:29 UTC] Number of nets: 34432 [13:29 UTC] [13:29 UTC] [INFO DRT-0167] List of default vias: [13:29 UTC] Layer Via2 [13:29 UTC] default via: Via2_YX [13:29 UTC] Layer Via3 [13:29 UTC] default via: Via3_XY [13:29 UTC] Layer TopVia1 [13:29 UTC] default via: TopVia1EWNS [13:29 UTC] [INFO DRT-0162] Library cell analysis. [13:29 UTC] [INFO DRT-0163] Instance analysis. [13:29 UTC] [INFO DRT-0164] Number of unique instances = 369. [13:29 UTC] [INFO DRT-0168] Init region query. [13:29 UTC] [INFO DRT-0024] Complete GatPoly. [13:29 UTC] [INFO DRT-0024] Complete Cont. [13:29 UTC] [INFO DRT-0024] Complete Metal1. [13:29 UTC] [INFO DRT-0024] Complete Via1. [13:29 UTC] [INFO DRT-0024] Complete Metal2. [13:29 UTC] [INFO DRT-0024] Complete Via2. [13:29 UTC] [INFO DRT-0024] Complete Metal3. [13:29 UTC] [INFO DRT-0024] Complete Via3. [13:29 UTC] [INFO DRT-0024] Complete Metal4. [13:29 UTC] [INFO DRT-0024] Complete TopVia1. [13:29 UTC] [INFO DRT-0024] Complete TopMetal1. [13:29 UTC] [INFO DRT-0033] GatPoly shape region query size = 0. [13:29 UTC] [INFO DRT-0033] Cont shape region query size = 0. [13:29 UTC] [INFO DRT-0033] Metal1 shape region query size = 926345. [13:29 UTC] [INFO DRT-0033] Via1 shape region query size = 16956. [13:29 UTC] [INFO DRT-0033] Metal2 shape region query size = 6582. [13:29 UTC] [INFO DRT-0033] Via2 shape region query size = 16956. [13:29 UTC] [INFO DRT-0033] Metal3 shape region query size = 9810. [13:29 UTC] [INFO DRT-0033] Via3 shape region query size = 16704. [13:29 UTC] [INFO DRT-0033] Metal4 shape region query size = 5759. [13:29 UTC] [INFO DRT-0033] TopVia1 shape region query size = 25491. [13:29 UTC] [INFO DRT-0033] TopMetal1 shape region query size = 2216. [13:29 UTC] [INFO DRT-0165] Start pin access. [13:29 UTC] [INFO DRT-0076] Complete 1000 pins. [13:29 UTC] [INFO DRT-0078] Complete 1403 pins. [13:29 UTC] [INFO DRT-0079] Complete 100 unique inst patterns. [13:29 UTC] [INFO DRT-0081] Complete 101 unique inst patterns. [13:31 UTC] [INFO DRT-0082] Complete 10000 groups. [13:32 UTC] [INFO DRT-0084] Complete 18583 groups. [13:32 UTC] #scanned instances = 34518 [13:32 UTC] #unique instances = 239 [13:32 UTC] #stdCellGenAp = 3969 [13:32 UTC] #stdCellValidPlanarAp = 0 [13:32 UTC] #stdCellValidViaAp = 3024 [13:32 UTC] #stdCellPinNoAp = 0 [13:32 UTC] #stdCellPinCnt = 117575 [13:32 UTC] #instTermValidViaApCnt = 0 [13:32 UTC] #macroGenAp = 5391 [13:32 UTC] #macroValidPlanarAp = 1065 [13:32 UTC] #macroValidViaAp = 145 [13:32 UTC] #macroNoAp = 0 [13:32 UTC] [INFO DRT-0166] Complete pin access. [13:32 UTC] [INFO DRT-0267] cpu time = 00:10:52, elapsed time = 00:02:44, memory = 846.62 (MB), peak = 870.95 (MB) [13:32 UTC] [INFO DRT-0156] guideIn read 100000 guides. [13:32 UTC] [INFO DRT-0156] guideIn read 200000 guides. [13:32 UTC] [13:32 UTC] [INFO DRT-0157] Number of guides: 279055 [13:32 UTC] [13:32 UTC] [INFO DRT-0169] Post process guides. [13:32 UTC] [INFO DRT-0176] GCELLGRID X 0 DO 266 STEP 7200 ; [13:32 UTC] [INFO DRT-0177] GCELLGRID Y 0 DO 266 STEP 7200 ; [13:32 UTC] [INFO DRT-0026] Complete 100000 origin guides. [13:32 UTC] [INFO DRT-0026] Complete 200000 origin guides. [13:32 UTC] [INFO DRT-0028] Complete GatPoly. [13:32 UTC] [INFO DRT-0028] Complete Cont. [13:32 UTC] [INFO DRT-0028] Complete Metal1. [13:32 UTC] [INFO DRT-0028] Complete Via1. [13:32 UTC] [INFO DRT-0028] Complete Metal2. [13:32 UTC] [INFO DRT-0028] Complete Via2. [13:32 UTC] [INFO DRT-0028] Complete Metal3. [13:32 UTC] [INFO DRT-0028] Complete Via3. [13:32 UTC] [INFO DRT-0028] Complete Metal4. [13:32 UTC] [INFO DRT-0028] Complete TopVia1. [13:32 UTC] [INFO DRT-0028] Complete TopMetal1. [13:32 UTC] [INFO DRT-0178] Init guide query. [13:32 UTC] [INFO DRT-0035] Complete GatPoly (guide). [13:32 UTC] [INFO DRT-0035] Complete Cont (guide). [13:32 UTC] [INFO DRT-0035] Complete Metal1 (guide). [13:32 UTC] [INFO DRT-0035] Complete Via1 (guide). [13:32 UTC] [INFO DRT-0035] Complete Metal2 (guide). [13:32 UTC] [INFO DRT-0035] Complete Via2 (guide). [13:32 UTC] [INFO DRT-0035] Complete Metal3 (guide). [13:32 UTC] [INFO DRT-0035] Complete Via3 (guide). [13:32 UTC] [INFO DRT-0035] Complete Metal4 (guide). [13:32 UTC] [INFO DRT-0035] Complete TopVia1 (guide). [13:32 UTC] [INFO DRT-0035] Complete TopMetal1 (guide). [13:32 UTC] [INFO DRT-0036] GatPoly guide region query size = 0. [13:32 UTC] [INFO DRT-0036] Cont guide region query size = 0. [13:32 UTC] [INFO DRT-0036] Metal1 guide region query size = 99489. [13:32 UTC] [INFO DRT-0036] Via1 guide region query size = 0. [13:32 UTC] [INFO DRT-0036] Metal2 guide region query size = 89177. [13:32 UTC] [INFO DRT-0036] Via2 guide region query size = 0. [13:32 UTC] [INFO DRT-0036] Metal3 guide region query size = 44001. [13:32 UTC] [INFO DRT-0036] Via3 guide region query size = 0. [13:32 UTC] [INFO DRT-0036] Metal4 guide region query size = 199. [13:32 UTC] [INFO DRT-0036] TopVia1 guide region query size = 0. [13:32 UTC] [INFO DRT-0036] TopMetal1 guide region query size = 18. [13:32 UTC] [INFO DRT-0179] Init gr pin query. [13:32 UTC] [INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:00, memory = 952.68 (MB), peak = 952.37 (MB) [13:32 UTC] [INFO DRT-0185] Post process initialize RPin region query. [13:32 UTC] [INFO DRT-0181] Start track assignment. [13:32 UTC] [INFO DRT-0184] Done with 89376 vertical wires in 6 frboxes and 143508 horizontal wires in 6 frboxes. [13:32 UTC] [INFO DRT-0186] Done with 34435 vertical wires in 6 frboxes and 19490 horizontal wires in 6 frboxes. [13:32 UTC] [INFO DRT-0182] Complete track assignment. [13:32 UTC] [INFO DRT-0267] cpu time = 00:00:24, elapsed time = 00:00:09, memory = 1587.66 (MB), peak = 1587.30 (MB) [13:32 UTC] [INFO DRT-0187] Start routing data preparation. [13:32 UTC] [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1587.78 (MB), peak = 1587.42 (MB) [13:32 UTC] [INFO DRT-0194] Start detail routing. [13:32 UTC] [INFO DRT-0195] Start 0th optimization iteration. [13:33 UTC] Completing 10% with 0 violations. [13:33 UTC] elapsed time = 00:00:49, memory = 1641.58 (MB). [13:36 UTC] Completing 20% with 0 violations. [13:36 UTC] elapsed time = 00:03:21, memory = 1911.60 (MB). [13:36 UTC] Completing 30% with 5396 violations. [13:36 UTC] elapsed time = 00:03:32, memory = 1937.20 (MB). [13:38 UTC] Completing 40% with 5396 violations. [13:38 UTC] elapsed time = 00:06:05, memory = 2048.54 (MB). [13:39 UTC] Completing 50% with 5396 violations. [13:39 UTC] elapsed time = 00:07:08, memory = 2013.88 (MB). [13:40 UTC] Completing 60% with 10993 violations. [13:40 UTC] elapsed time = 00:08:17, memory = 2083.29 (MB). [13:43 UTC] Completing 70% with 10993 violations. [13:43 UTC] elapsed time = 00:10:49, memory = 2134.67 (MB). [13:43 UTC] Completing 80% with 16394 violations. [13:43 UTC] elapsed time = 00:11:04, memory = 2103.42 (MB). [13:46 UTC] Completing 90% with 16394 violations. [13:46 UTC] elapsed time = 00:13:37, memory = 2211.71 (MB). [13:47 UTC] Completing 100% with 21639 violations. [13:47 UTC] elapsed time = 00:14:40, memory = 2186.09 (MB). [13:47 UTC] [INFO DRT-0199] Number of violations = 26606. [13:47 UTC] Viol/Layer Metal1 Via1 Metal2 Via2 Metal3 Via3 Metal4 To..a1 To..l1 [13:47 UTC] Cut Spacing 0 7 0 0 0 0 0 0 0 [13:47 UTC] Metal Spacing 0 0 5090 0 98 0 4 0 0 [13:47 UTC] Min Area 0 0 1 0 0 0 0 0 0 [13:47 UTC] Min Width 0 0 0 0 0 0 0 0 3 [13:47 UTC] NS Metal 0 0 4 0 0 0 0 0 0 [13:47 UTC] Off Grid 0 0 2 0 0 0 0 0 0 [13:47 UTC] Recheck 75 0 3369 0 1465 0 58 0 0 [13:47 UTC] Short 0 62 14633 76 1628 18 7 3 3 [13:47 UTC] [INFO DRT-0267] cpu time = 00:58:01, elapsed time = 00:14:41, memory = 2218.46 (MB), peak = 2341.93 (MB) [13:47 UTC] Total wire length = 1763131 um. [13:47 UTC] Total wire length on LAYER Metal1 = 0 um. [13:47 UTC] Total wire length on LAYER Metal2 = 857616 um. [13:47 UTC] Total wire length on LAYER Metal3 = 848433 um. [13:47 UTC] Total wire length on LAYER Metal4 = 55709 um. [13:47 UTC] Total wire length on LAYER TopMetal1 = 1372 um. [13:47 UTC] Total number of vias = 258141. [13:47 UTC] Up-via summary (total 258141): [13:47 UTC] [13:47 UTC] ------------------ [13:47 UTC] GatPoly 0 [13:47 UTC] Metal1 118020 [13:47 UTC] Metal2 129667 [13:47 UTC] Metal3 10419 [13:47 UTC] Metal4 35 [13:47 UTC] ------------------ [13:47 UTC] 258141 [13:47 UTC] [13:47 UTC] [13:47 UTC] [INFO DRT-0195] Start 1st optimization iteration. [13:48 UTC] Completing 10% with 26606 violations. [13:48 UTC] elapsed time = 00:00:44, memory = 2303.71 (MB). [13:50 UTC] Completing 20% with 26606 violations. [13:50 UTC] elapsed time = 00:02:45, memory = 2287.80 (MB). [13:50 UTC] Completing 30% with 23982 violations. [13:50 UTC] elapsed time = 00:03:05, memory = 2223.41 (MB). [13:52 UTC] Completing 40% with 23982 violations. [13:52 UTC] elapsed time = 00:04:51, memory = 2333.30 (MB). [13:53 UTC] Completing 50% with 23982 violations. [13:53 UTC] elapsed time = 00:06:00, memory = 2371.11 (MB). [13:54 UTC] Completing 60% with 21761 violations. [13:54 UTC] elapsed time = 00:06:52, memory = 2393.14 (MB). [13:56 UTC] Completing 70% with 21761 violations. [13:56 UTC] elapsed time = 00:09:03, memory = 2369.45 (MB). [13:56 UTC] Completing 80% with 19219 violations. [13:56 UTC] elapsed time = 00:09:13, memory = 2333.98 (MB). [13:58 UTC] Completing 90% with 19219 violations. [13:58 UTC] elapsed time = 00:11:16, memory = 2413.41 (MB). [13:59 UTC] Completing 100% with 16356 violations. [13:59 UTC] elapsed time = 00:12:16, memory = 2345.12 (MB). [13:59 UTC] [INFO DRT-0199] Number of violations = 16356. [13:59 UTC] Viol/Layer Metal2 Metal3 Metal4 [13:59 UTC] Metal Spacing 4923 49 0 [13:59 UTC] Recheck 1 3 0 [13:59 UTC] Short 10727 643 10 [13:59 UTC] [INFO DRT-0267] cpu time = 00:48:10, elapsed time = 00:12:17, memory = 2345.12 (MB), peak = 2474.60 (MB) [13:59 UTC] Total wire length = 1754668 um. [13:59 UTC] Total wire length on LAYER Metal1 = 0 um. [13:59 UTC] Total wire length on LAYER Metal2 = 843385 um. [13:59 UTC] Total wire length on LAYER Metal3 = 845463 um. [13:59 UTC] Total wire length on LAYER Metal4 = 64492 um. [13:59 UTC] Total wire length on LAYER TopMetal1 = 1327 um. [13:59 UTC] Total number of vias = 257250. [13:59 UTC] Up-via summary (total 257250): [13:59 UTC] [13:59 UTC] ------------------ [13:59 UTC] GatPoly 0 [13:59 UTC] Metal1 117990 [13:59 UTC] Metal2 127483 [13:59 UTC] Metal3 11743 [13:59 UTC] Metal4 34 [13:59 UTC] ------------------ [13:59 UTC] 257250 [13:59 UTC] [13:59 UTC] [13:59 UTC] [INFO DRT-0195] Start 2nd optimization iteration. [14:00 UTC] Completing 10% with 16356 violations. [14:00 UTC] elapsed time = 00:00:48, memory = 2379.66 (MB). [14:02 UTC] Completing 20% with 16356 violations. [14:02 UTC] elapsed time = 00:02:50, memory = 2382.41 (MB). [14:02 UTC] Completing 30% with 16300 violations. [14:02 UTC] elapsed time = 00:03:07, memory = 2346.29 (MB). [14:04 UTC] Completing 40% with 16300 violations. [14:04 UTC] elapsed time = 00:04:49, memory = 2368.59 (MB). [14:05 UTC] Completing 50% with 16300 violations. [14:05 UTC] elapsed time = 00:06:07, memory = 2421.85 (MB). [14:06 UTC] Completing 60% with 15863 violations. [14:06 UTC] elapsed time = 00:06:42, memory = 2379.18 (MB). [14:08 UTC] Completing 70% with 15863 violations. [14:08 UTC] elapsed time = 00:08:43, memory = 2395.70 (MB). [14:08 UTC] Completing 80% with 15452 violations. [14:08 UTC] elapsed time = 00:09:00, memory = 2353.31 (MB). [14:10 UTC] Completing 90% with 15452 violations. [14:10 UTC] elapsed time = 00:10:51, memory = 2376.17 (MB). [14:11 UTC] Completing 100% with 15130 violations. [14:11 UTC] elapsed time = 00:11:58, memory = 2353.31 (MB). [14:11 UTC] [INFO DRT-0199] Number of violations = 15130. [14:11 UTC] Viol/Layer Metal2 Metal3 Metal4 [14:11 UTC] Metal Spacing 4725 55 0 [14:11 UTC] Short 9686 654 10 [14:11 UTC] [INFO DRT-0267] cpu time = 00:46:43, elapsed time = 00:11:59, memory = 2353.31 (MB), peak = 2509.60 (MB) [14:11 UTC] Total wire length = 1751966 um. [14:11 UTC] Total wire length on LAYER Metal1 = 0 um. [14:11 UTC] Total wire length on LAYER Metal2 = 840083 um. [14:11 UTC] Total wire length on LAYER Metal3 = 844812 um. [14:11 UTC] Total wire length on LAYER Metal4 = 65705 um. [14:11 UTC] Total wire length on LAYER TopMetal1 = 1365 um. [14:11 UTC] Total number of vias = 256620. [14:11 UTC] Up-via summary (total 256620): [14:11 UTC] [14:11 UTC] ------------------ [14:11 UTC] GatPoly 0 [14:11 UTC] Metal1 118001 [14:11 UTC] Metal2 127079 [14:11 UTC] Metal3 11504 [14:11 UTC] Metal4 36 [14:11 UTC] ------------------ [14:11 UTC] 256620 [14:11 UTC] [14:11 UTC] [14:11 UTC] [INFO DRT-0195] Start 3rd optimization iteration. [14:11 UTC] Completing 10% with 15130 violations. [14:11 UTC] elapsed time = 00:00:13, memory = 2370.03 (MB). [14:12 UTC] Completing 20% with 15130 violations. [14:12 UTC] elapsed time = 00:00:55, memory = 2461.63 (MB). [14:12 UTC] Completing 30% with 11615 violations. [14:12 UTC] elapsed time = 00:01:01, memory = 2298.54 (MB). [14:13 UTC] Completing 40% with 11615 violations. [14:13 UTC] elapsed time = 00:01:44, memory = 2439.66 (MB). [14:13 UTC] Completing 50% with 11615 violations. [14:13 UTC] elapsed time = 00:02:09, memory = 2298.54 (MB). [14:14 UTC] Completing 60% with 7865 violations. [14:14 UTC] elapsed time = 00:02:31, memory = 2401.05 (MB). [14:14 UTC] Completing 70% with 7865 violations. [14:14 UTC] elapsed time = 00:03:16, memory = 2441.35 (MB). [14:15 UTC] Completing 80% with 4128 violations. [14:15 UTC] elapsed time = 00:03:23, memory = 2288.07 (MB). [14:15 UTC] Completing 90% with 4128 violations. [14:15 UTC] elapsed time = 00:04:05, memory = 2369.97 (MB). [14:16 UTC] Completing 100% with 539 violations. [14:16 UTC] elapsed time = 00:04:24, memory = 2234.75 (MB). [14:16 UTC] [INFO DRT-0199] Number of violations = 539. [14:16 UTC] Viol/Layer Metal2 Via2 Metal3 Metal4 [14:16 UTC] Cut Spacing 0 1 0 0 [14:16 UTC] Metal Spacing 291 0 4 0 [14:16 UTC] Short 211 0 23 9 [14:16 UTC] [INFO DRT-0267] cpu time = 00:16:23, elapsed time = 00:04:24, memory = 2234.75 (MB), peak = 2521.38 (MB) [14:16 UTC] Total wire length = 1746538 um. [14:16 UTC] Total wire length on LAYER Metal1 = 0 um. [14:16 UTC] Total wire length on LAYER Metal2 = 752087 um. [14:16 UTC] Total wire length on LAYER Metal3 = 845412 um. [14:16 UTC] Total wire length on LAYER Metal4 = 147411 um. [14:16 UTC] Total wire length on LAYER TopMetal1 = 1627 um. [14:16 UTC] Total number of vias = 263440. [14:16 UTC] Up-via summary (total 263440): [14:16 UTC] [14:16 UTC] ------------------ [14:16 UTC] GatPoly 0 [14:16 UTC] Metal1 118004 [14:16 UTC] Metal2 126770 [14:16 UTC] Metal3 18615 [14:16 UTC] Metal4 51 [14:16 UTC] ------------------ [14:16 UTC] 263440 [14:16 UTC] [14:16 UTC] [14:16 UTC] [INFO DRT-0195] Start 4th optimization iteration. [14:16 UTC] Completing 10% with 539 violations. [14:16 UTC] elapsed time = 00:00:00, memory = 2234.75 (MB). [14:16 UTC] Completing 20% with 539 violations. [14:16 UTC] elapsed time = 00:00:04, memory = 2377.32 (MB). [14:16 UTC] Completing 30% with 497 violations. [14:16 UTC] elapsed time = 00:00:14, memory = 2265.23 (MB). [14:16 UTC] Completing 40% with 497 violations. [14:16 UTC] elapsed time = 00:00:16, memory = 2344.57 (MB). [14:16 UTC] Completing 50% with 497 violations. [14:16 UTC] elapsed time = 00:00:18, memory = 2387.35 (MB). [14:16 UTC] Completing 60% with 346 violations. [14:16 UTC] elapsed time = 00:00:18, memory = 2265.23 (MB). [14:16 UTC] Completing 70% with 346 violations. [14:16 UTC] elapsed time = 00:00:27, memory = 2407.10 (MB). [14:17 UTC] Completing 80% with 143 violations. [14:17 UTC] elapsed time = 00:00:56, memory = 2266.40 (MB). [14:17 UTC] Completing 90% with 143 violations. [14:17 UTC] elapsed time = 00:00:58, memory = 2342.21 (MB). [14:17 UTC] Completing 100% with 61 violations. [14:17 UTC] elapsed time = 00:01:00, memory = 2266.40 (MB). [14:17 UTC] [INFO DRT-0199] Number of violations = 61. [14:17 UTC] Viol/Layer Metal2 [14:17 UTC] Metal Spacing 45 [14:17 UTC] Short 16 [14:17 UTC] [INFO DRT-0267] cpu time = 00:02:09, elapsed time = 00:01:00, memory = 2266.40 (MB), peak = 2521.38 (MB) [14:17 UTC] Total wire length = 1746447 um. [14:17 UTC] Total wire length on LAYER Metal1 = 0 um. [14:17 UTC] Total wire length on LAYER Metal2 = 751592 um. [14:17 UTC] Total wire length on LAYER Metal3 = 845411 um. [14:17 UTC] Total wire length on LAYER Metal4 = 147775 um. [14:17 UTC] Total wire length on LAYER TopMetal1 = 1668 um. [14:17 UTC] Total number of vias = 263388. [14:17 UTC] Up-via summary (total 263388): [14:17 UTC] [14:17 UTC] ------------------ [14:17 UTC] GatPoly 0 [14:17 UTC] Metal1 118004 [14:17 UTC] Metal2 126747 [14:17 UTC] Metal3 18584 [14:17 UTC] Metal4 53 [14:17 UTC] ------------------ [14:17 UTC] 263388 [14:17 UTC] [14:17 UTC] [14:17 UTC] [INFO DRT-0195] Start 5th optimization iteration. [14:17 UTC] Completing 10% with 61 violations. [14:17 UTC] elapsed time = 00:00:00, memory = 2266.40 (MB). [14:17 UTC] Completing 20% with 61 violations. [14:17 UTC] elapsed time = 00:00:00, memory = 2266.40 (MB). [14:17 UTC] Completing 30% with 38 violations. [14:17 UTC] elapsed time = 00:00:09, memory = 2266.40 (MB). [14:17 UTC] Completing 40% with 38 violations. [14:17 UTC] elapsed time = 00:00:09, memory = 2266.40 (MB). [14:17 UTC] Completing 50% with 38 violations. [14:17 UTC] elapsed time = 00:00:09, memory = 2266.40 (MB). [14:17 UTC] Completing 60% with 37 violations. [14:17 UTC] elapsed time = 00:00:11, memory = 2266.40 (MB). [14:17 UTC] Completing 70% with 37 violations. [14:17 UTC] elapsed time = 00:00:11, memory = 2266.40 (MB). [14:17 UTC] Completing 80% with 20 violations. [14:17 UTC] elapsed time = 00:00:12, memory = 2266.40 (MB). [14:17 UTC] Completing 90% with 20 violations. [14:17 UTC] elapsed time = 00:00:12, memory = 2266.40 (MB). [14:17 UTC] Completing 100% with 10 violations. [14:17 UTC] elapsed time = 00:00:15, memory = 2266.40 (MB). [14:17 UTC] [INFO DRT-0199] Number of violations = 10. [14:17 UTC] Viol/Layer Metal2 [14:17 UTC] Metal Spacing 10 [14:17 UTC] [INFO DRT-0267] cpu time = 00:00:24, elapsed time = 00:00:15, memory = 2266.59 (MB), peak = 2521.38 (MB) [14:17 UTC] Total wire length = 1746503 um. [14:17 UTC] Total wire length on LAYER Metal1 = 0 um. [14:17 UTC] Total wire length on LAYER Metal2 = 751473 um. [14:17 UTC] Total wire length on LAYER Metal3 = 845414 um. [14:17 UTC] Total wire length on LAYER Metal4 = 147951 um. [14:17 UTC] Total wire length on LAYER TopMetal1 = 1664 um. [14:17 UTC] Total number of vias = 263389. [14:17 UTC] Up-via summary (total 263389): [14:17 UTC] [14:17 UTC] ------------------ [14:17 UTC] GatPoly 0 [14:17 UTC] Metal1 118004 [14:17 UTC] Metal2 126734 [14:17 UTC] Metal3 18598 [14:17 UTC] Metal4 53 [14:17 UTC] ------------------ [14:17 UTC] 263389 [14:17 UTC] [14:17 UTC] [14:17 UTC] [INFO DRT-0195] Start 6th stubborn tiles iteration. [14:17 UTC] Completing 10% with 10 violations. [14:17 UTC] elapsed time = 00:00:21, memory = 2368.64 (MB). [14:18 UTC] Completing 20% with 10 violations. [14:18 UTC] elapsed time = 00:00:38, memory = 2376.02 (MB). [14:18 UTC] Completing 30% with 10 violations. [14:18 UTC] elapsed time = 00:00:55, memory = 2374.54 (MB). [14:18 UTC] Completing 40% with 10 violations. [14:18 UTC] elapsed time = 00:01:15, memory = 2394.07 (MB). [14:18 UTC] Completing 50% with 10 violations. [14:18 UTC] elapsed time = 00:01:30, memory = 2266.59 (MB). [14:19 UTC] Completing 60% with 6 violations. [14:19 UTC] elapsed time = 00:02:32, memory = 2448.07 (MB). [14:20 UTC] Completing 70% with 6 violations. [14:20 UTC] elapsed time = 00:03:35, memory = 2448.45 (MB). [14:21 UTC] Completing 80% with 6 violations. [14:21 UTC] elapsed time = 00:04:31, memory = 2452.28 (MB). [14:22 UTC] Completing 90% with 6 violations. [14:22 UTC] elapsed time = 00:05:29, memory = 2429.63 (MB). [14:23 UTC] Completing 100% with 4 violations. [14:23 UTC] elapsed time = 00:06:27, memory = 2266.81 (MB). [14:23 UTC] [INFO DRT-0199] Number of violations = 4. [14:23 UTC] Viol/Layer Metal2 Metal3 [14:23 UTC] Metal Spacing 2 2 [14:23 UTC] [INFO DRT-0267] cpu time = 00:24:46, elapsed time = 00:06:27, memory = 2266.81 (MB), peak = 2523.46 (MB) [14:23 UTC] Total wire length = 1746532 um. [14:23 UTC] Total wire length on LAYER Metal1 = 0 um. [14:23 UTC] Total wire length on LAYER Metal2 = 751499 um. [14:23 UTC] Total wire length on LAYER Metal3 = 845433 um. [14:23 UTC] Total wire length on LAYER Metal4 = 147948 um. [14:23 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [14:23 UTC] Total number of vias = 263396. [14:23 UTC] Up-via summary (total 263396): [14:23 UTC] [14:23 UTC] ------------------ [14:23 UTC] GatPoly 0 [14:23 UTC] Metal1 118004 [14:23 UTC] Metal2 126734 [14:23 UTC] Metal3 18607 [14:23 UTC] Metal4 51 [14:23 UTC] ------------------ [14:23 UTC] 263396 [14:23 UTC] [14:23 UTC] [14:23 UTC] [INFO DRT-0195] Start 7th stubborn tiles iteration. [14:24 UTC] Completing 10% with 4 violations. [14:24 UTC] elapsed time = 00:00:33, memory = 2413.97 (MB). [14:24 UTC] Completing 20% with 4 violations. [14:24 UTC] elapsed time = 00:00:56, memory = 2445.08 (MB). [14:25 UTC] Completing 30% with 4 violations. [14:25 UTC] elapsed time = 00:01:32, memory = 2421.96 (MB). [14:25 UTC] Completing 40% with 4 violations. [14:25 UTC] elapsed time = 00:02:09, memory = 2449.93 (MB). [14:26 UTC] Completing 50% with 4 violations. [14:26 UTC] elapsed time = 00:02:36, memory = 2457.99 (MB). [14:26 UTC] Completing 60% with 4 violations. [14:26 UTC] elapsed time = 00:03:04, memory = 2456.73 (MB). [14:27 UTC] Completing 70% with 4 violations. [14:27 UTC] elapsed time = 00:03:26, memory = 2377.09 (MB). [14:27 UTC] Completing 80% with 4 violations. [14:27 UTC] elapsed time = 00:03:53, memory = 2412.93 (MB). [14:28 UTC] Completing 90% with 4 violations. [14:28 UTC] elapsed time = 00:04:19, memory = 2441.16 (MB). [14:28 UTC] Completing 100% with 4 violations. [14:28 UTC] elapsed time = 00:04:42, memory = 2266.81 (MB). [14:28 UTC] [INFO DRT-0199] Number of violations = 4. [14:28 UTC] Viol/Layer Metal2 Metal3 [14:28 UTC] Metal Spacing 2 2 [14:28 UTC] [INFO DRT-0267] cpu time = 00:17:56, elapsed time = 00:04:42, memory = 2266.81 (MB), peak = 2563.95 (MB) [14:28 UTC] Total wire length = 1746532 um. [14:28 UTC] Total wire length on LAYER Metal1 = 0 um. [14:28 UTC] Total wire length on LAYER Metal2 = 751499 um. [14:28 UTC] Total wire length on LAYER Metal3 = 845433 um. [14:28 UTC] Total wire length on LAYER Metal4 = 147948 um. [14:28 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [14:28 UTC] Total number of vias = 263396. [14:28 UTC] Up-via summary (total 263396): [14:28 UTC] [14:28 UTC] ------------------ [14:28 UTC] GatPoly 0 [14:28 UTC] Metal1 118004 [14:28 UTC] Metal2 126734 [14:28 UTC] Metal3 18607 [14:28 UTC] Metal4 51 [14:28 UTC] ------------------ [14:28 UTC] 263396 [14:28 UTC] [14:28 UTC] [14:28 UTC] [INFO DRT-0200] Skipping iteration 8 [14:28 UTC] [INFO DRT-0200] Skipping iteration 9 [14:28 UTC] [INFO DRT-0195] Start 10th stubborn tiles iteration. [14:29 UTC] Completing 10% with 4 violations. [14:29 UTC] elapsed time = 00:00:30, memory = 2483.92 (MB). [14:29 UTC] Completing 20% with 4 violations. [14:29 UTC] elapsed time = 00:01:13, memory = 2464.23 (MB). [14:30 UTC] Completing 30% with 4 violations. [14:30 UTC] elapsed time = 00:01:55, memory = 2476.97 (MB). [14:31 UTC] Completing 40% with 4 violations. [14:31 UTC] elapsed time = 00:02:30, memory = 2469.01 (MB). [14:31 UTC] Completing 50% with 4 violations. [14:31 UTC] elapsed time = 00:03:18, memory = 2474.29 (MB). [14:32 UTC] Completing 60% with 4 violations. [14:32 UTC] elapsed time = 00:03:58, memory = 2425.98 (MB). [14:32 UTC] Completing 70% with 4 violations. [14:32 UTC] elapsed time = 00:04:23, memory = 2464.00 (MB). [14:33 UTC] Completing 80% with 4 violations. [14:33 UTC] elapsed time = 00:04:41, memory = 2446.05 (MB). [14:33 UTC] Completing 90% with 4 violations. [14:33 UTC] elapsed time = 00:05:11, memory = 2444.05 (MB). [14:34 UTC] Completing 100% with 4 violations. [14:34 UTC] elapsed time = 00:05:41, memory = 2266.81 (MB). [14:34 UTC] [INFO DRT-0199] Number of violations = 4. [14:34 UTC] Viol/Layer Metal2 Metal3 [14:34 UTC] Metal Spacing 2 2 [14:34 UTC] [INFO DRT-0267] cpu time = 00:21:42, elapsed time = 00:05:41, memory = 2266.81 (MB), peak = 2610.33 (MB) [14:34 UTC] Total wire length = 1746532 um. [14:34 UTC] Total wire length on LAYER Metal1 = 0 um. [14:34 UTC] Total wire length on LAYER Metal2 = 751499 um. [14:34 UTC] Total wire length on LAYER Metal3 = 845433 um. [14:34 UTC] Total wire length on LAYER Metal4 = 147948 um. [14:34 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [14:34 UTC] Total number of vias = 263396. [14:34 UTC] Up-via summary (total 263396): [14:34 UTC] [14:34 UTC] ------------------ [14:34 UTC] GatPoly 0 [14:34 UTC] Metal1 118004 [14:34 UTC] Metal2 126734 [14:34 UTC] Metal3 18607 [14:34 UTC] Metal4 51 [14:34 UTC] ------------------ [14:34 UTC] 263396 [14:34 UTC] [14:34 UTC] [14:34 UTC] [INFO DRT-0200] Skipping iteration 11 [14:34 UTC] [INFO DRT-0200] Skipping iteration 12 [14:34 UTC] [INFO DRT-0200] Skipping iteration 13 [14:34 UTC] [INFO DRT-0200] Skipping iteration 14 [14:34 UTC] [INFO DRT-0195] Start 15th stubborn tiles iteration. [14:34 UTC] Completing 10% with 4 violations. [14:34 UTC] elapsed time = 00:00:30, memory = 2464.33 (MB). [14:35 UTC] Completing 20% with 4 violations. [14:35 UTC] elapsed time = 00:01:12, memory = 2497.28 (MB). [14:36 UTC] Completing 30% with 4 violations. [14:36 UTC] elapsed time = 00:01:53, memory = 2477.94 (MB). [14:36 UTC] Completing 40% with 4 violations. [14:36 UTC] elapsed time = 00:02:28, memory = 2469.71 (MB). [14:37 UTC] Completing 50% with 4 violations. [14:37 UTC] elapsed time = 00:03:13, memory = 2505.15 (MB). [14:38 UTC] Completing 60% with 4 violations. [14:38 UTC] elapsed time = 00:03:52, memory = 2454.52 (MB). [14:38 UTC] Completing 70% with 4 violations. [14:38 UTC] elapsed time = 00:04:16, memory = 2467.89 (MB). [14:38 UTC] Completing 80% with 4 violations. [14:38 UTC] elapsed time = 00:04:35, memory = 2447.51 (MB). [14:39 UTC] Completing 90% with 4 violations. [14:39 UTC] elapsed time = 00:05:08, memory = 2417.47 (MB). [14:39 UTC] Completing 100% with 4 violations. [14:39 UTC] elapsed time = 00:05:31, memory = 2266.81 (MB). [14:39 UTC] [INFO DRT-0199] Number of violations = 4. [14:39 UTC] Viol/Layer Metal2 Metal3 [14:39 UTC] Metal Spacing 2 2 [14:39 UTC] [INFO DRT-0267] cpu time = 00:21:10, elapsed time = 00:05:31, memory = 2266.81 (MB), peak = 2610.33 (MB) [14:39 UTC] Total wire length = 1746532 um. [14:39 UTC] Total wire length on LAYER Metal1 = 0 um. [14:39 UTC] Total wire length on LAYER Metal2 = 751499 um. [14:39 UTC] Total wire length on LAYER Metal3 = 845433 um. [14:39 UTC] Total wire length on LAYER Metal4 = 147948 um. [14:39 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [14:39 UTC] Total number of vias = 263396. [14:39 UTC] Up-via summary (total 263396): [14:39 UTC] [14:39 UTC] ------------------ [14:39 UTC] GatPoly 0 [14:39 UTC] Metal1 118004 [14:39 UTC] Metal2 126734 [14:39 UTC] Metal3 18607 [14:39 UTC] Metal4 51 [14:39 UTC] ------------------ [14:39 UTC] 263396 [14:39 UTC] [14:39 UTC] [14:39 UTC] [INFO DRT-0200] Skipping iteration 16 [14:39 UTC] [INFO DRT-0195] Start 17th optimization iteration. [14:39 UTC] Completing 10% with 4 violations. [14:39 UTC] elapsed time = 00:00:00, memory = 2266.81 (MB). [14:39 UTC] Completing 20% with 4 violations. [14:39 UTC] elapsed time = 00:00:00, memory = 2266.81 (MB). [14:39 UTC] Completing 30% with 4 violations. [14:39 UTC] elapsed time = 00:00:11, memory = 2266.81 (MB). [14:39 UTC] Completing 40% with 4 violations. [14:39 UTC] elapsed time = 00:00:11, memory = 2266.81 (MB). [14:39 UTC] Completing 50% with 4 violations. [14:39 UTC] elapsed time = 00:00:11, memory = 2266.81 (MB). [14:39 UTC] Completing 60% with 4 violations. [14:39 UTC] elapsed time = 00:00:11, memory = 2266.81 (MB). [14:39 UTC] Completing 70% with 4 violations. [14:39 UTC] elapsed time = 00:00:11, memory = 2266.81 (MB). [14:39 UTC] Completing 80% with 4 violations. [14:39 UTC] elapsed time = 00:00:11, memory = 2266.81 (MB). [14:39 UTC] Completing 90% with 4 violations. [14:39 UTC] elapsed time = 00:00:11, memory = 2266.81 (MB). [14:39 UTC] Completing 100% with 4 violations. [14:39 UTC] elapsed time = 00:00:11, memory = 2266.81 (MB). [14:39 UTC] [INFO DRT-0199] Number of violations = 4. [14:39 UTC] Viol/Layer Metal2 Metal3 [14:39 UTC] Metal Spacing 2 2 [14:39 UTC] [INFO DRT-0267] cpu time = 00:00:11, elapsed time = 00:00:11, memory = 2266.81 (MB), peak = 2610.33 (MB) [14:39 UTC] Total wire length = 1746532 um. [14:39 UTC] Total wire length on LAYER Metal1 = 0 um. [14:39 UTC] Total wire length on LAYER Metal2 = 751499 um. [14:39 UTC] Total wire length on LAYER Metal3 = 845433 um. [14:39 UTC] Total wire length on LAYER Metal4 = 147948 um. [14:39 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [14:39 UTC] Total number of vias = 263396. [14:39 UTC] Up-via summary (total 263396): [14:39 UTC] [14:39 UTC] ------------------ [14:39 UTC] GatPoly 0 [14:39 UTC] Metal1 118004 [14:39 UTC] Metal2 126734 [14:39 UTC] Metal3 18607 [14:39 UTC] Metal4 51 [14:39 UTC] ------------------ [14:39 UTC] 263396 [14:39 UTC] [14:39 UTC] [14:39 UTC] [INFO DRT-0195] Start 18th stubborn tiles iteration. [14:40 UTC] Completing 10% with 4 violations. [14:40 UTC] elapsed time = 00:00:51, memory = 2477.59 (MB). [14:41 UTC] Completing 20% with 4 violations. [14:41 UTC] elapsed time = 00:01:18, memory = 2516.38 (MB). [14:42 UTC] Completing 30% with 4 violations. [14:42 UTC] elapsed time = 00:02:11, memory = 2523.02 (MB). [14:42 UTC] Completing 40% with 4 violations. [14:42 UTC] elapsed time = 00:02:53, memory = 2516.60 (MB). [14:43 UTC] Completing 50% with 4 violations. [14:43 UTC] elapsed time = 00:03:49, memory = 2510.64 (MB). [14:44 UTC] Completing 60% with 4 violations. [14:44 UTC] elapsed time = 00:04:18, memory = 2457.25 (MB). [14:44 UTC] Completing 70% with 4 violations. [14:44 UTC] elapsed time = 00:04:58, memory = 2479.03 (MB). [14:45 UTC] Completing 80% with 4 violations. [14:45 UTC] elapsed time = 00:05:21, memory = 2484.29 (MB). [14:45 UTC] Completing 90% with 4 violations. [14:45 UTC] elapsed time = 00:05:44, memory = 2459.38 (MB). [14:46 UTC] Completing 100% with 2 violations. [14:46 UTC] elapsed time = 00:06:08, memory = 2266.81 (MB). [14:46 UTC] [INFO DRT-0199] Number of violations = 2. [14:46 UTC] Viol/Layer Metal2 [14:46 UTC] Metal Spacing 2 [14:46 UTC] [INFO DRT-0267] cpu time = 00:24:08, elapsed time = 00:06:08, memory = 2266.81 (MB), peak = 2629.88 (MB) [14:46 UTC] Total wire length = 1746531 um. [14:46 UTC] Total wire length on LAYER Metal1 = 0 um. [14:46 UTC] Total wire length on LAYER Metal2 = 751494 um. [14:46 UTC] Total wire length on LAYER Metal3 = 845430 um. [14:46 UTC] Total wire length on LAYER Metal4 = 147954 um. [14:46 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [14:46 UTC] Total number of vias = 263395. [14:46 UTC] Up-via summary (total 263395): [14:46 UTC] [14:46 UTC] ------------------ [14:46 UTC] GatPoly 0 [14:46 UTC] Metal1 118004 [14:46 UTC] Metal2 126729 [14:46 UTC] Metal3 18611 [14:46 UTC] Metal4 51 [14:46 UTC] ------------------ [14:46 UTC] 263395 [14:46 UTC] [14:46 UTC] [14:46 UTC] [INFO DRT-0195] Start 19th stubborn tiles iteration. [14:46 UTC] Completing 10% with 2 violations. [14:46 UTC] elapsed time = 00:00:36, memory = 2457.62 (MB). [14:47 UTC] Completing 20% with 2 violations. [14:47 UTC] elapsed time = 00:01:18, memory = 2466.40 (MB). [14:48 UTC] Completing 30% with 2 violations. [14:48 UTC] elapsed time = 00:02:11, memory = 2522.93 (MB). [14:49 UTC] Completing 40% with 2 violations. [14:49 UTC] elapsed time = 00:03:00, memory = 2516.84 (MB). [14:49 UTC] Completing 50% with 2 violations. [14:49 UTC] elapsed time = 00:03:34, memory = 2510.90 (MB). [14:50 UTC] Completing 60% with 2 violations. [14:50 UTC] elapsed time = 00:04:12, memory = 2423.94 (MB). [14:50 UTC] Completing 70% with 2 violations. [14:50 UTC] elapsed time = 00:04:41, memory = 2478.76 (MB). [14:51 UTC] Completing 80% with 2 violations. [14:51 UTC] elapsed time = 00:05:15, memory = 2495.11 (MB). [14:51 UTC] Completing 90% with 2 violations. [14:51 UTC] elapsed time = 00:05:32, memory = 2432.87 (MB). [14:52 UTC] Completing 100% with 2 violations. [14:52 UTC] elapsed time = 00:06:01, memory = 2266.81 (MB). [14:52 UTC] [INFO DRT-0199] Number of violations = 2. [14:52 UTC] Viol/Layer Metal2 [14:52 UTC] Short 2 [14:52 UTC] [INFO DRT-0267] cpu time = 00:23:36, elapsed time = 00:06:02, memory = 2266.81 (MB), peak = 2629.88 (MB) [14:52 UTC] Total wire length = 1746529 um. [14:52 UTC] Total wire length on LAYER Metal1 = 0 um. [14:52 UTC] Total wire length on LAYER Metal2 = 751496 um. [14:52 UTC] Total wire length on LAYER Metal3 = 845426 um. [14:52 UTC] Total wire length on LAYER Metal4 = 147954 um. [14:52 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [14:52 UTC] Total number of vias = 263395. [14:52 UTC] Up-via summary (total 263395): [14:52 UTC] [14:52 UTC] ------------------ [14:52 UTC] GatPoly 0 [14:52 UTC] Metal1 118004 [14:52 UTC] Metal2 126729 [14:52 UTC] Metal3 18611 [14:52 UTC] Metal4 51 [14:52 UTC] ------------------ [14:52 UTC] 263395 [14:52 UTC] [14:52 UTC] [14:52 UTC] [INFO DRT-0195] Start 20th stubborn tiles iteration. [14:52 UTC] Completing 10% with 2 violations. [14:52 UTC] elapsed time = 00:00:35, memory = 2497.65 (MB). [14:53 UTC] Completing 20% with 2 violations. [14:53 UTC] elapsed time = 00:01:16, memory = 2510.40 (MB). [14:53 UTC] Completing 30% with 2 violations. [14:53 UTC] elapsed time = 00:01:40, memory = 2515.11 (MB). [14:54 UTC] Completing 40% with 2 violations. [14:54 UTC] elapsed time = 00:02:27, memory = 2519.01 (MB). [14:55 UTC] Completing 50% with 2 violations. [14:55 UTC] elapsed time = 00:03:03, memory = 2428.80 (MB). [14:55 UTC] Completing 60% with 2 violations. [14:55 UTC] elapsed time = 00:03:41, memory = 2497.11 (MB). [14:56 UTC] Completing 70% with 2 violations. [14:56 UTC] elapsed time = 00:04:03, memory = 2417.10 (MB). [14:56 UTC] Completing 80% with 2 violations. [14:56 UTC] elapsed time = 00:04:35, memory = 2495.96 (MB). [14:57 UTC] Completing 90% with 2 violations. [14:57 UTC] elapsed time = 00:05:00, memory = 2475.96 (MB). [14:57 UTC] Completing 100% with 2 violations. [14:57 UTC] elapsed time = 00:05:30, memory = 2266.81 (MB). [14:57 UTC] [INFO DRT-0199] Number of violations = 2. [14:57 UTC] Viol/Layer Metal2 [14:57 UTC] Metal Spacing 2 [14:57 UTC] [INFO DRT-0267] cpu time = 00:21:13, elapsed time = 00:05:30, memory = 2266.81 (MB), peak = 2648.71 (MB) [14:57 UTC] Total wire length = 1746525 um. [14:57 UTC] Total wire length on LAYER Metal1 = 0 um. [14:57 UTC] Total wire length on LAYER Metal2 = 751495 um. [14:57 UTC] Total wire length on LAYER Metal3 = 845426 um. [14:57 UTC] Total wire length on LAYER Metal4 = 147951 um. [14:57 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [14:57 UTC] Total number of vias = 263393. [14:57 UTC] Up-via summary (total 263393): [14:57 UTC] [14:57 UTC] ------------------ [14:57 UTC] GatPoly 0 [14:57 UTC] Metal1 118004 [14:57 UTC] Metal2 126729 [14:57 UTC] Metal3 18609 [14:57 UTC] Metal4 51 [14:57 UTC] ------------------ [14:57 UTC] 263393 [14:57 UTC] [14:57 UTC] [14:57 UTC] [INFO DRT-0200] Skipping iteration 21 [14:57 UTC] [INFO DRT-0200] Skipping iteration 22 [14:57 UTC] [INFO DRT-0195] Start 23rd stubborn tiles iteration. [14:58 UTC] Completing 10% with 2 violations. [14:58 UTC] elapsed time = 00:00:23, memory = 2381.05 (MB). [14:58 UTC] Completing 20% with 2 violations. [14:58 UTC] elapsed time = 00:00:43, memory = 2425.43 (MB). [14:58 UTC] Completing 30% with 2 violations. [14:58 UTC] elapsed time = 00:01:20, memory = 2446.96 (MB). [14:59 UTC] Completing 40% with 2 violations. [14:59 UTC] elapsed time = 00:01:50, memory = 2421.12 (MB). [15:00 UTC] Completing 50% with 2 violations. [15:00 UTC] elapsed time = 00:02:22, memory = 2448.49 (MB). [15:00 UTC] Completing 60% with 2 violations. [15:00 UTC] elapsed time = 00:02:48, memory = 2435.75 (MB). [15:00 UTC] Completing 70% with 2 violations. [15:00 UTC] elapsed time = 00:03:21, memory = 2432.43 (MB). [15:01 UTC] Completing 80% with 2 violations. [15:01 UTC] elapsed time = 00:03:38, memory = 2390.21 (MB). [15:01 UTC] Completing 90% with 2 violations. [15:01 UTC] elapsed time = 00:03:58, memory = 2446.12 (MB). [15:02 UTC] Completing 100% with 2 violations. [15:02 UTC] elapsed time = 00:04:23, memory = 2270.35 (MB). [15:02 UTC] [INFO DRT-0199] Number of violations = 2. [15:02 UTC] Viol/Layer Metal2 [15:02 UTC] Metal Spacing 2 [15:02 UTC] [INFO DRT-0267] cpu time = 00:16:46, elapsed time = 00:04:23, memory = 2270.35 (MB), peak = 2648.71 (MB) [15:02 UTC] Total wire length = 1746525 um. [15:02 UTC] Total wire length on LAYER Metal1 = 0 um. [15:02 UTC] Total wire length on LAYER Metal2 = 751495 um. [15:02 UTC] Total wire length on LAYER Metal3 = 845426 um. [15:02 UTC] Total wire length on LAYER Metal4 = 147951 um. [15:02 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [15:02 UTC] Total number of vias = 263393. [15:02 UTC] Up-via summary (total 263393): [15:02 UTC] [15:02 UTC] ------------------ [15:02 UTC] GatPoly 0 [15:02 UTC] Metal1 118004 [15:02 UTC] Metal2 126729 [15:02 UTC] Metal3 18609 [15:02 UTC] Metal4 51 [15:02 UTC] ------------------ [15:02 UTC] 263393 [15:02 UTC] [15:02 UTC] [15:02 UTC] [INFO DRT-0195] Start 24th stubborn tiles iteration. [15:02 UTC] Completing 10% with 2 violations. [15:02 UTC] elapsed time = 00:00:32, memory = 2460.40 (MB). [15:03 UTC] Completing 20% with 2 violations. [15:03 UTC] elapsed time = 00:01:13, memory = 2528.86 (MB). [15:03 UTC] Completing 30% with 2 violations. [15:03 UTC] elapsed time = 00:01:40, memory = 2522.66 (MB). [15:04 UTC] Completing 40% with 2 violations. [15:04 UTC] elapsed time = 00:02:22, memory = 2530.12 (MB). [15:04 UTC] Completing 50% with 2 violations. [15:04 UTC] elapsed time = 00:02:47, memory = 2517.04 (MB). [15:05 UTC] Completing 60% with 2 violations. [15:05 UTC] elapsed time = 00:03:32, memory = 2466.46 (MB). [15:05 UTC] Completing 70% with 2 violations. [15:05 UTC] elapsed time = 00:03:52, memory = 2416.64 (MB). [15:06 UTC] Completing 80% with 2 violations. [15:06 UTC] elapsed time = 00:04:27, memory = 2466.39 (MB). [15:06 UTC] Completing 90% with 2 violations. [15:06 UTC] elapsed time = 00:04:54, memory = 2502.08 (MB). [15:07 UTC] Completing 100% with 2 violations. [15:07 UTC] elapsed time = 00:05:19, memory = 2270.35 (MB). [15:07 UTC] [INFO DRT-0199] Number of violations = 2. [15:07 UTC] Viol/Layer Metal2 [15:07 UTC] Metal Spacing 2 [15:07 UTC] [INFO DRT-0267] cpu time = 00:20:23, elapsed time = 00:05:19, memory = 2270.35 (MB), peak = 2654.36 (MB) [15:07 UTC] Total wire length = 1746544 um. [15:07 UTC] Total wire length on LAYER Metal1 = 0 um. [15:07 UTC] Total wire length on LAYER Metal2 = 751496 um. [15:07 UTC] Total wire length on LAYER Metal3 = 845437 um. [15:07 UTC] Total wire length on LAYER Metal4 = 147959 um. [15:07 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [15:07 UTC] Total number of vias = 263397. [15:07 UTC] Up-via summary (total 263397): [15:07 UTC] [15:07 UTC] ------------------ [15:07 UTC] GatPoly 0 [15:07 UTC] Metal1 118004 [15:07 UTC] Metal2 126729 [15:07 UTC] Metal3 18613 [15:07 UTC] Metal4 51 [15:07 UTC] ------------------ [15:07 UTC] 263397 [15:07 UTC] [15:07 UTC] [15:07 UTC] [INFO DRT-0195] Start 25th optimization iteration. [15:07 UTC] Completing 10% with 2 violations. [15:07 UTC] elapsed time = 00:00:00, memory = 2270.35 (MB). [15:07 UTC] Completing 20% with 2 violations. [15:07 UTC] elapsed time = 00:00:00, memory = 2270.35 (MB). [15:07 UTC] Completing 30% with 2 violations. [15:07 UTC] elapsed time = 00:00:00, memory = 2270.35 (MB). [15:07 UTC] Completing 40% with 2 violations. [15:07 UTC] elapsed time = 00:00:00, memory = 2270.35 (MB). [15:07 UTC] Completing 50% with 2 violations. [15:07 UTC] elapsed time = 00:00:00, memory = 2270.35 (MB). [15:07 UTC] Completing 60% with 2 violations. [15:07 UTC] elapsed time = 00:00:00, memory = 2270.35 (MB). [15:07 UTC] Completing 70% with 2 violations. [15:07 UTC] elapsed time = 00:00:00, memory = 2270.35 (MB). [15:07 UTC] Completing 80% with 2 violations. [15:07 UTC] elapsed time = 00:00:06, memory = 2270.35 (MB). [15:07 UTC] Completing 90% with 2 violations. [15:07 UTC] elapsed time = 00:00:06, memory = 2270.35 (MB). [15:07 UTC] Completing 100% with 2 violations. [15:07 UTC] elapsed time = 00:00:06, memory = 2270.35 (MB). [15:07 UTC] [INFO DRT-0199] Number of violations = 2. [15:07 UTC] Viol/Layer Metal2 [15:07 UTC] Metal Spacing 2 [15:07 UTC] [INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:06, memory = 2270.35 (MB), peak = 2654.36 (MB) [15:07 UTC] Total wire length = 1746544 um. [15:07 UTC] Total wire length on LAYER Metal1 = 0 um. [15:07 UTC] Total wire length on LAYER Metal2 = 751496 um. [15:07 UTC] Total wire length on LAYER Metal3 = 845437 um. [15:07 UTC] Total wire length on LAYER Metal4 = 147959 um. [15:07 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [15:07 UTC] Total number of vias = 263397. [15:07 UTC] Up-via summary (total 263397): [15:07 UTC] [15:07 UTC] ------------------ [15:07 UTC] GatPoly 0 [15:07 UTC] Metal1 118004 [15:07 UTC] Metal2 126729 [15:07 UTC] Metal3 18613 [15:07 UTC] Metal4 51 [15:07 UTC] ------------------ [15:07 UTC] 263397 [15:07 UTC] [15:07 UTC] [15:07 UTC] [INFO DRT-0195] Start 26th stubborn tiles iteration. [15:08 UTC] Completing 10% with 2 violations. [15:08 UTC] elapsed time = 00:00:50, memory = 2514.06 (MB). [15:09 UTC] Completing 20% with 2 violations. [15:09 UTC] elapsed time = 00:01:35, memory = 2536.15 (MB). [15:09 UTC] Completing 30% with 2 violations. [15:09 UTC] elapsed time = 00:01:58, memory = 2491.79 (MB). [15:09 UTC] Completing 40% with 2 violations. [15:09 UTC] elapsed time = 00:02:28, memory = 2530.80 (MB). [15:11 UTC] Completing 50% with 2 violations. [15:11 UTC] elapsed time = 00:03:34, memory = 2524.99 (MB). [15:11 UTC] Completing 60% with 2 violations. [15:11 UTC] elapsed time = 00:04:00, memory = 2508.74 (MB). [15:12 UTC] Completing 70% with 2 violations. [15:12 UTC] elapsed time = 00:04:38, memory = 2481.90 (MB). [15:12 UTC] Completing 80% with 2 violations. [15:12 UTC] elapsed time = 00:05:09, memory = 2507.77 (MB). [15:13 UTC] Completing 90% with 2 violations. [15:13 UTC] elapsed time = 00:05:50, memory = 2510.63 (MB). [15:13 UTC] Completing 100% with 2 violations. [15:13 UTC] elapsed time = 00:06:08, memory = 2270.40 (MB). [15:13 UTC] [INFO DRT-0199] Number of violations = 2. [15:13 UTC] Viol/Layer Metal2 [15:13 UTC] Metal Spacing 2 [15:13 UTC] [INFO DRT-0267] cpu time = 00:23:53, elapsed time = 00:06:08, memory = 2270.40 (MB), peak = 2654.36 (MB) [15:13 UTC] Total wire length = 1746544 um. [15:13 UTC] Total wire length on LAYER Metal1 = 0 um. [15:13 UTC] Total wire length on LAYER Metal2 = 751496 um. [15:13 UTC] Total wire length on LAYER Metal3 = 845437 um. [15:13 UTC] Total wire length on LAYER Metal4 = 147959 um. [15:13 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [15:13 UTC] Total number of vias = 263397. [15:13 UTC] Up-via summary (total 263397): [15:13 UTC] [15:13 UTC] ------------------ [15:13 UTC] GatPoly 0 [15:13 UTC] Metal1 118004 [15:13 UTC] Metal2 126729 [15:13 UTC] Metal3 18613 [15:13 UTC] Metal4 51 [15:13 UTC] ------------------ [15:13 UTC] 263397 [15:13 UTC] [15:13 UTC] [15:13 UTC] [INFO DRT-0200] Skipping iteration 27 [15:13 UTC] [INFO DRT-0200] Skipping iteration 28 [15:13 UTC] [INFO DRT-0200] Skipping iteration 29 [15:13 UTC] [INFO DRT-0195] Start 30th stubborn tiles iteration. [15:14 UTC] Completing 10% with 2 violations. [15:14 UTC] elapsed time = 00:00:26, memory = 2449.21 (MB). [15:14 UTC] Completing 20% with 2 violations. [15:14 UTC] elapsed time = 00:00:42, memory = 2434.04 (MB). [15:14 UTC] Completing 30% with 2 violations. [15:14 UTC] elapsed time = 00:01:17, memory = 2459.49 (MB). [15:15 UTC] Completing 40% with 2 violations. [15:15 UTC] elapsed time = 00:01:37, memory = 2464.33 (MB). [15:15 UTC] Completing 50% with 2 violations. [15:15 UTC] elapsed time = 00:02:00, memory = 2432.01 (MB). [15:15 UTC] Completing 60% with 2 violations. [15:15 UTC] elapsed time = 00:02:19, memory = 2380.76 (MB). [15:16 UTC] Completing 70% with 2 violations. [15:16 UTC] elapsed time = 00:02:51, memory = 2440.77 (MB). [15:16 UTC] Completing 80% with 2 violations. [15:16 UTC] elapsed time = 00:03:08, memory = 2421.79 (MB). [15:16 UTC] Completing 90% with 2 violations. [15:16 UTC] elapsed time = 00:03:16, memory = 2398.53 (MB). [15:17 UTC] Completing 100% with 2 violations. [15:17 UTC] elapsed time = 00:03:29, memory = 2270.46 (MB). [15:17 UTC] [INFO DRT-0199] Number of violations = 2. [15:17 UTC] Viol/Layer Metal2 [15:17 UTC] Metal Spacing 2 [15:17 UTC] [INFO DRT-0267] cpu time = 00:13:42, elapsed time = 00:03:29, memory = 2270.46 (MB), peak = 2654.36 (MB) [15:17 UTC] Total wire length = 1746544 um. [15:17 UTC] Total wire length on LAYER Metal1 = 0 um. [15:17 UTC] Total wire length on LAYER Metal2 = 751496 um. [15:17 UTC] Total wire length on LAYER Metal3 = 845437 um. [15:17 UTC] Total wire length on LAYER Metal4 = 147959 um. [15:17 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [15:17 UTC] Total number of vias = 263397. [15:17 UTC] Up-via summary (total 263397): [15:17 UTC] [15:17 UTC] ------------------ [15:17 UTC] GatPoly 0 [15:17 UTC] Metal1 118004 [15:17 UTC] Metal2 126729 [15:17 UTC] Metal3 18613 [15:17 UTC] Metal4 51 [15:17 UTC] ------------------ [15:17 UTC] 263397 [15:17 UTC] [15:17 UTC] [15:17 UTC] [INFO DRT-0195] Start 31st stubborn tiles iteration. [15:18 UTC] Completing 10% with 2 violations. [15:18 UTC] elapsed time = 00:01:01, memory = 2515.19 (MB). [15:18 UTC] Completing 20% with 2 violations. [15:18 UTC] elapsed time = 00:01:34, memory = 2540.03 (MB). [15:19 UTC] Completing 30% with 2 violations. [15:19 UTC] elapsed time = 00:01:57, memory = 2494.16 (MB). [15:19 UTC] Completing 40% with 2 violations. [15:19 UTC] elapsed time = 00:02:29, memory = 2532.31 (MB). [15:20 UTC] Completing 50% with 2 violations. [15:20 UTC] elapsed time = 00:03:22, memory = 2529.45 (MB). [15:21 UTC] Completing 60% with 2 violations. [15:21 UTC] elapsed time = 00:03:53, memory = 2511.49 (MB). [15:21 UTC] Completing 70% with 2 violations. [15:21 UTC] elapsed time = 00:04:29, memory = 2455.32 (MB). [15:22 UTC] Completing 80% with 2 violations. [15:22 UTC] elapsed time = 00:04:58, memory = 2475.82 (MB). [15:22 UTC] Completing 90% with 2 violations. [15:22 UTC] elapsed time = 00:05:39, memory = 2510.75 (MB). [15:23 UTC] Completing 100% with 2 violations. [15:23 UTC] elapsed time = 00:06:01, memory = 2270.46 (MB). [15:23 UTC] [INFO DRT-0199] Number of violations = 2. [15:23 UTC] Viol/Layer Metal2 [15:23 UTC] Metal Spacing 2 [15:23 UTC] [INFO DRT-0267] cpu time = 00:23:25, elapsed time = 00:06:01, memory = 2270.46 (MB), peak = 2654.36 (MB) [15:23 UTC] Total wire length = 1746544 um. [15:23 UTC] Total wire length on LAYER Metal1 = 0 um. [15:23 UTC] Total wire length on LAYER Metal2 = 751496 um. [15:23 UTC] Total wire length on LAYER Metal3 = 845437 um. [15:23 UTC] Total wire length on LAYER Metal4 = 147959 um. [15:23 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [15:23 UTC] Total number of vias = 263397. [15:23 UTC] Up-via summary (total 263397): [15:23 UTC] [15:23 UTC] ------------------ [15:23 UTC] GatPoly 0 [15:23 UTC] Metal1 118004 [15:23 UTC] Metal2 126729 [15:23 UTC] Metal3 18613 [15:23 UTC] Metal4 51 [15:23 UTC] ------------------ [15:23 UTC] 263397 [15:23 UTC] [15:23 UTC] [15:23 UTC] [INFO DRT-0200] Skipping iteration 32 [15:23 UTC] [INFO DRT-0195] Start 33rd optimization iteration. [15:23 UTC] Completing 10% with 2 violations. [15:23 UTC] elapsed time = 00:00:00, memory = 2270.46 (MB). [15:23 UTC] Completing 20% with 2 violations. [15:23 UTC] elapsed time = 00:00:00, memory = 2270.46 (MB). [15:23 UTC] Completing 30% with 0 violations. [15:23 UTC] elapsed time = 00:00:00, memory = 2270.46 (MB). [15:23 UTC] Completing 40% with 0 violations. [15:23 UTC] elapsed time = 00:00:00, memory = 2270.46 (MB). [15:23 UTC] Completing 50% with 0 violations. [15:23 UTC] elapsed time = 00:00:00, memory = 2270.46 (MB). [15:23 UTC] Completing 60% with 0 violations. [15:23 UTC] elapsed time = 00:00:00, memory = 2270.46 (MB). [15:23 UTC] Completing 70% with 0 violations. [15:23 UTC] elapsed time = 00:00:00, memory = 2270.46 (MB). [15:23 UTC] Completing 80% with 0 violations. [15:23 UTC] elapsed time = 00:00:00, memory = 2270.46 (MB). [15:23 UTC] Completing 90% with 0 violations. [15:23 UTC] elapsed time = 00:00:00, memory = 2270.46 (MB). [15:23 UTC] Completing 100% with 0 violations. [15:23 UTC] elapsed time = 00:00:00, memory = 2270.46 (MB). [15:23 UTC] [INFO DRT-0199] Number of violations = 0. [15:23 UTC] [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 2270.46 (MB), peak = 2654.36 (MB) [15:23 UTC] Total wire length = 1746533 um. [15:23 UTC] Total wire length on LAYER Metal1 = 0 um. [15:23 UTC] Total wire length on LAYER Metal2 = 751459 um. [15:23 UTC] Total wire length on LAYER Metal3 = 845430 um. [15:23 UTC] Total wire length on LAYER Metal4 = 147992 um. [15:23 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [15:23 UTC] Total number of vias = 263377. [15:23 UTC] Up-via summary (total 263377): [15:23 UTC] [15:23 UTC] ------------------ [15:23 UTC] GatPoly 0 [15:23 UTC] Metal1 118004 [15:23 UTC] Metal2 126722 [15:23 UTC] Metal3 18600 [15:23 UTC] Metal4 51 [15:23 UTC] ------------------ [15:23 UTC] 263377 [15:23 UTC] [15:23 UTC] [15:23 UTC] [INFO DRT-0198] Complete detail routing. [15:23 UTC] Total wire length = 1746533 um. [15:23 UTC] Total wire length on LAYER Metal1 = 0 um. [15:23 UTC] Total wire length on LAYER Metal2 = 751459 um. [15:23 UTC] Total wire length on LAYER Metal3 = 845430 um. [15:23 UTC] Total wire length on LAYER Metal4 = 147992 um. [15:23 UTC] Total wire length on LAYER TopMetal1 = 1651 um. [15:23 UTC] Total number of vias = 263377. [15:23 UTC] Up-via summary (total 263377): [15:23 UTC] [15:23 UTC] ------------------ [15:23 UTC] GatPoly 0 [15:23 UTC] Metal1 118004 [15:23 UTC] Metal2 126722 [15:23 UTC] Metal3 18600 [15:23 UTC] Metal4 51 [15:23 UTC] ------------------ [15:23 UTC] 263377 [15:23 UTC] [15:23 UTC] [15:23 UTC] [INFO DRT-0267] cpu time = 07:04:57, elapsed time = 01:50:26, memory = 2270.46 (MB), peak = 2654.36 (MB) [15:23 UTC] [15:23 UTC] [INFO DRT-0180] Post processing. [15:23 UTC] Saving detailed route [15:23 UTC] Saving checkpoint 04_croc.routed [15:23 UTC] Time: 6911.327746 sec deltaT: 6854.705690000001 [15:23 UTC] saving image to reports/04_croc.routed.png [15:23 UTC] [WARNING GUI-0076] QStandardPaths: runtime directory '/tmp/runtime-default' is not owned by UID 1001, but a directory permissions 0777 owned by UID 0 GID 0 [15:23 UTC] [WARNING GUI-0076] QStandardPaths: runtime directory '/tmp/runtime-default' is not owned by UID 1001, but a directory permissions 0777 owned by UID 0 GID 0 [15:23 UTC] ############################################################################### [15:23 UTC] # Stage 04 complete: Checkpoint saved to save/04_croc.routed.zip [15:23 UTC] ###############################################################################