Running program: ../sw/bin/test/test_uart.hex
ClkFrequency:         20MHz
UartRealBaudRate:     113636
@     42100ns | [JTAG] Initialization success
@     42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@     94650ns | [JTAG] Read 0x12345678 from 0x10000000
@     94650ns | [JTAG] Read back correct data
@     94650ns | [JTAG] Loading binary from ../sw/bin/test/test_uart.hex
@     96950ns | [JTAG] Writing to memory @10000000 
@    106150ns | [JTAG] Writing to memory @1000000c 
@    119950ns | [JTAG] Writing to memory @10000020 
@   1479250ns | [CORE] Waking core via CLINT msip
@   1479250ns | [JTAG] Writing 0x00000001 to 0x02040000
@   1502300ns | [JTAG] Halting hart 0... 
@   1515650ns | [JTAG] Halted
@   1517950ns | [JTAG] Resumed hart 0 
@   1517950ns | [CORE] Wait for end of code...
@   1818950ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
@   1818975ns | [UART] TX
- S i m u l a t i o n   R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 2ms; walltime 0.909 s; speed 1.301 ms/s
- Verilator: cpu 1.398 s on 1 threads; alloced 548 MB