Module stream_fifo_optimal_wrap

Optimal implementation of a stream FIFO based on the common cells modules.

Selects the smaller and faster spill register if the depth is 2 and the FIFO if

the depth is >2. Throws an error for the meaningless configurations depth 0 and 1.

AXI Package

Parameters

Depth: int unsigned

Depth can be arbitrary from 2 to 2**32

type_t: type

Type of the FIFO

PrintInfo: bit

Print information when the simulation launches

AddrDepth: int unsigned

Ports

clk_i: input logic

rst_ni: input logic

flush_i: input logic

testmode_i: input logic

usage_o: output logic [AddrDepth-1:0]

data_i: input type_t

valid_i: input logic

ready_o: output logic

data_o: output type_t

valid_o: output logic

ready_i: input logic