Module spill_register_flushable

A register with handshakes that completely cuts any combinational paths

between the input and output. This spill register can be flushed.

Parameters

`T: type`

`Bypass: bit`

Ports

`clk_i: input logic`

`rst_ni: input logic`

`valid_i: input logic`

`flush_i: input logic`

`ready_o: output logic`

`data_i: input T`

`valid_o: output logic`

`ready_i: input logic`

`data_o: output T`

Signals

`a_data_q: T`

`b_data_q: T`